Universal Logic Gate Research Articles

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT

This paper analyzes the efficiency of different FPGA architectures consisting of Hybrid logic blocks (HLB) formed with Look-up Tables (LUTs) and Universal Logic Gates (ULGs). Pure LUT-based architectures induce area overhead and a longer delay. A ULG is designed to realize an efficient architecture compared to pure LUT-based architectures. Using this ULG and LUT in different proportions, HLBs are designed. The Field Programmable Gate Array (FPGA) architectures containing these proposed HLB structures are analyzed using various Microelectronics Centre of North Carolina (MCNC) benchmark circuits and compared with the performance of the existing designs. The result shows that the proposed architecture design can save a tremendous amount of time in overall flow and routing along with area improvements.

Universal all-optical zero-bias logic gates in silicon photonics

Universal all-optical (optical input – optical output) logic gates, realized in a commercial foundry silicon photonics process, are reported. Microring resonator modulator and zero-biased stacked photodiodes are used to create the required optical input-output nonlinear transfer function for optical gate realizations. Several logic gate functions, specifically NOR which is a universal logic gate that can be used to implement any logic, are demonstrated. Logic operation on 10 Mbps data streams is demonstrated using universal optical logic gates without requiring any electrical supply voltage. The total optical power required for one such universal logic gate is 160 µW.

Ultrafast reverse saturable absorption and all-optical computing with boron dipyrromethene (BODIPY) chromophore derivatives

Ultrafast reverse saturable absorption (RSA) in chromophore-based borondipyrro-methenes (BODIPYs) derivatives, 1,7-Diphenyl-3,5-bis(9,9-dimethyl-9H-fluoren-2-yl)-boron-diuoride-azadipyrromethene (ZL-61) and 1,7-Diphenyl-3,5-bis(4-(1,2,2-triphenyl-vinyl)phenyl)-boron-diuoride azadipyrromethene (ZL-22), has been theoretically analyzed with femtosecond (fs) laser pulses at 800 nm and 850 nm. The results are in good agreement with the reported experimental results. The effect of input pulse intensity, pulse width, nonlinear absorption (NLA) coefficients, sample thickness and laser pulse shaping on transmittance has been studied and optimized for high contrast and low-power operation. All-optical fs NOT and the universal NOR and NAND Boolean logic gates have been designed with ZL-61 and ZL-22. The logic gates with top-hat input pulse profile have a sharp switch ON/OFF time compared to the Gaussian input laser profile. Ultrafast operation at relatively low pump intensities opens up exciting prospects for the applicability of BODIPY derivatives for ultrafast low-power all-optical computing and information processing.

Room temperature, cascadable, all-optical polariton universal gates

Today, almost all information processing is performed using electronic logic circuits operating at several gigahertz frequency. All-optical logic holds the promise to allow for up to three orders of magnitude higher speed. Whereas essential all-optical transistor functionalities were demonstrated across a range of platforms, utilising them to implement a complete Boolean logic gate set and in particular negation, i.e. switching off an optical signal with another, weaker, optical signal, poses a major challenge. Here, we realize a cascadable NOT gate by introducing the concept of non-ground-state polariton amplification in organic semiconductor microcavities under non-resonant optical excitation. We unravel the importance of vibron-mediated stimulated scattering in room temperature operation of the inverter. Moreover, we extend the concept to a multi-input universal NOR logic gate, where in the presence of any of the input signals non-ground-state amplification supersedes spontaneous ground-state condensation, resulting in a NOR gate with ~1 ps switching time. The realisation of an ultrafast universal logic gate constitutes an essential step for more complex optical circuitry that could boost information processing applications.

Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach

This paper introduces a new design for 3 × 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm2 and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm2 and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.

Single-step parity check gate set for quantum error correction

A key requirement for an effective quantum error correction (QEC) scheme is that the physical qubits have error rates below a certain threshold. The value of this threshold depends on the details of the specific QEC scheme, and its hardware-level implementation. This is especially important with parity-check circuits, which are the fundamental building blocks of QEC codes. The standard way of constructing the parity check circuit is using a universal set of gates, namely sequential CNOT gates, single-qubit rotations and measurements. We exploit the insight that a QEC code does not require universal logic gates, but can be simplified to perform the sole task of error detection and correction. By building gates that are fundamental to QEC, we can boost the threshold and ease the experimental demands on the physical hardware. We present a rigorous formalism for constructing and verifying the error behavior of these gates, linking the physical measurement of a process matrix to the abstract error models commonly used in QEC analysis. This allows experimentalists to directly map the gates used in their systems to thresholds derived for a broad-class of QEC codes. We give an example of these new constructions using the model system of two nuclear spins, coupled to an electron spin, showing the potential benefits of redesigning fundamental gate sets using QEC primitives, rather than traditional gate sets reliant on simple single and two-qubit gates.

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

AbstractDirect printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

Skyrmion based universal logic gates and computation operation

Swirling spin configurations with a non-trivial topological state are popularly known as magnetic skyrmions. They are often observed in magnetic thin films with perpendicular magnetic anisotropy and Dzyaloshinskii–Moriya interaction (DMI). Due to their small size and non-collinear spin texture, they are being considered as a potential candidate for spintronic devices such as data storage devices, and logic-based devices. These skyrmions have distinct properties and interactions, that can be utilized to control their movement by applying an external electric current. In this work, we have successfully demonstrated the operation of skyrmion-based universal NAND and NOR logic gates. We have further performed arithmetic addition of two and three single-bit by using a half and full adder, fabricated based on the XOR and AND gates. We have observed that the presence of only uniform DMI is not enough to achieve all logic operations. The presence of a negative DMI at the edges is crucial in achieving proper logic operations. The findings are very important for the realization of skyrmion-based logic and computational operations.

Inverter and Universal Gates Implementation Using Novel Core Insulator Double Gate (CIDG) MOSFETs

The Core Insulator Double Gate (CIDG) MOSFET has been explored for digital applications in which the presence of core insulator diminishes the bulk conduction and reduces the off state current. The drain currents of n- and p-type CIDG MOSFETs are matched by tuning gate work functions to deliver the symmetrical pull-up and pull-down characteristics. The inverter and universal logic gates (NAND and NOR) have been designed and implemented to show the usability of the CIDG MOSFETs for digital applications. The DC and transient characteristic of the inverter along with Static Noise Margin (SNM) and time delay parameters have been examined. The designed Inverter shows steeper voltage transfer characteristics, reduced short circuit power dissipation and improved noise immunity. The CIDG MOSFET based NAND and NOR gate implementation and validation by transient analysis have been shown for the first time to the best knowledge of the authors. Also, the rise and fall times of the inverter, NAND and NOR gates have been found to be improved as compared to the DG MOSFET counterparts. The present analysis establishes that CIDG MOSFETs are useful in designing digital circuits with improved performance.

Simulation of universal optical logic gates under energy sharing collisions of Manakov solitons and fulfillment of practical optical logic criteria.

The universal optical logic gates, namely, nand and nor gates, have been theoretically simulated by employing the energy sharing collision of bright optical solitons in the Manakov system, governing pulse propagation in a highly birefringent fiber. Further, we also realize the two-input optical logic gates, such as and, or, xor, xnor, for completeness of our scheme. Interestingly, our idea behind the simulation naturally satisfies all the criteria for practical optical logic, which in turn displays the strength and versatility of our theoretical simulation of universal optical logic gates. Hence, our approach paves the way for the experimentalists to create a new avenue in this direction if the energy sharing collisions of Manakov solitons are experimentally realized in the future.

Ultrafast nonlinear absorption in MoTe2 and MoTe2/MoS2 nanocomposite films and its application to all-optical logic gates

We present a detailed theoretical analysis of ultrafast saturable absorption (SA) and reverse SA (RSA) in MoTe2 nano-films with femtosecond (fs) laser pulses at 800 nm. A transition from RSA to SA occurs on increasing the thickness from 30 nm to 80 nm at a constant pump intensity of 141 GW cm−2. On the other hand, a transition from SA to RSA occurs upon increasing the pump intensity in an 80 nm thick MoTe2 nano-film. Theoretical results are in good agreement with reported experimental results. The effect of pump pulse intensity, pulse width, nonlinear absorption coefficient and sample thickness has been studied to optimize the SA ↔ RSA transition. The results for low-power and high contrast all-optical switching in MoTe2 nano-films have been used to design all-optical fs NOT, OR, AND, as well as the universal all-optical NOR and NAND logic gates. The SA behavior of MoTe2/MoS2 nanocomposite films has been used to design all-optical AND and OR logic gates. The nanocomposite films of MoTe2/MoS2 possess a larger nonlinear optical response in comparison to MoTe2 and MoS2 nano-films and, therefore, all-optical logic gates designed using nanocomposite films result in a good switching contrast compared to pure MoTe2 nano-films. Ultrafast operation at relatively low pump intensities demonstrates the applicability of MoTe2 and MoTe2/MoS2 nano-films for ultrafast all-optical information processing.

Experimental realisation of multi-qubit gates using electron paramagnetic resonance

Quantum information processing promises to revolutionise computing; quantum algorithms have been discovered that address common tasks significantly more efficiently than their classical counterparts. For a physical system to be a viable quantum computer it must be possible to initialise its quantum state, to realise a set of universal quantum logic gates, including at least one multi-qubit gate, and to make measurements of qubit states. Molecular Electron Spin Qubits (MESQs) have been proposed to fulfil these criteria, as their bottom-up synthesis should facilitate tuning properties as desired and the reproducible production of multi-MESQ structures. Here we explore how to perform a two-qubit entangling gate on a multi-MESQ system, and how to readout the state via quantum state tomography. We propose methods of accomplishing both procedures using multifrequency pulse Electron Paramagnetic Resonance (EPR) and apply them to a model MESQ structure consisting of two nitroxide spin centres. Our results confirm the methodological principles and shed light on the experimental hurdles which must be overcome to realise a demonstration of controlled entanglement on this system.

Toward a Voltage Reconfigurable Logic Gate

Currently, novel approaches are being developed to overcome the imminent Moore's law failure. The techniques attempt to gain greater computing power by reducing the number of transistors. This work presents the simulation of a reconfigurable voltage logic gate based on the equation of a plane. The proposal is achieved by using two variables of the equation of a plane as inputs and the other as output. The proposed circuit can perform the NAND and NOR logic gates, known as universal logic gates. The simulation results show the feasibility of the proposed reconfigurable logic gate. Also, the presented circuit is compatible with the transistor-transistor-logic and can be modified to implement other logic gates by changing a voltage level.

Assessment of a universal logic gate and a full adder circuit based on CMOS-memristor technology

The study of memristor-based digital logic circuits is a new approach in non-conventional computation frameworks because of the memristor's properties, especially the ability to store data and perform logic operations. Using memristors, in this work, we have analyzed in terms of variability basic AND/OR Universal Logic Gates (ULG) and a Full adder implementation at the circuit-level in LT-spice. We first implement and calibrate a memristor's model with data obtained from IV curves of HfO2-based ReRAM to do it. The data demonstrate that although buffers are used to restore the signal, memristors variability affects the output voltage and the circuit's performance.

Trumpet is an operating system for simple and robust cell-free biocomputing

Biological computation is becoming a viable and fast-growing alternative to traditional electronic computing. Here we present a biocomputing technology called Trumpet: Transcriptional RNA Universal Multi-Purpose GatE PlaTform. Trumpet combines the simplicity and robustness of the simplest in vitro biocomputing methods, adding signal amplification and programmability, while avoiding common shortcomings of live cell-based biocomputing solutions. We have demonstrated the use of Trumpet to build all universal Boolean logic gates. We have also built a web-based platform for designing Trumpet gates and created a primitive processor by networking several gates as a proof-of-principle for future development. The Trumpet offers a change of paradigm in biocomputing, providing an efficient and easily programmable biological logic gate operating system.

Logical Blocks for Fault-Tolerant Topological Quantum Computation

Logical gates constitute the building blocks of fault-tolerant quantum computation. While quantum error-corrected memories have been extensively studied in the literature, explicit constructions and detailed analyses of thresholds and resource overheads of universal logical gate sets have so far been limited. In this paper, we present a comprehensive framework for universal fault-tolerant logic motivated by the combined need for platform-independent logical gate definitions, flexible and scalable tools for numerical analysis, and exploration of novel schemes for universal logic that improve resource overheads. Central to our framework is the description of logical gates holistically in a way which treats space and time on a similar footing. Focusing on schemes based on surface codes, we introduce explicit, but platform-independent representations of topological logic gates -- called logical blocks -- and generate new, overhead-efficient methods for universal quantum computation. As a specific example, we propose fault-tolerant schemes based on surface codes concatenated with more general low-density parity check (LDPC) codes. The logical blocks framework enables a convenient mapping from an abstract description of the logical gate to a precise set of physical instructions for both circuit-based and fusion-based quantum computation (FBQC). Using this, we numerically simulate a surface-code-based universal gate set implemented with FBQC, and verify that their thresholds are consistent with the bulk memory threshold. We find that boundaries, defects, and twists can significantly impact the logical error rate scaling, with periodic boundary conditions potentially halving the resource requirements. Motivated by the favorable logical error rates for boundaryless computation, we introduce a novel computational scheme based on the teleportation of twists that may offer further resource reductions.

Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors’s knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

Universal quantum computation with symmetric qubit clusters coupled to an environment

One of the most challenging problems for the realization of a scalable quantum computer is to design a physical device that keeps the error rate for each quantum processing operation low. These errors can originate from the accuracy of quantum manipulation, such as the sweeping of a gate voltage in solid state qubits or the duration of a laser pulse in optical schemes. Errors also result from decoherence, which is often regarded as more crucial in the sense that it is inherent to the quantum system, being fundamentally a consequence of the coupling to the external environment. Grouping small collections of qubits into clusters with symmetries may serve to protect parts of the calculation from decoherence. In this work, we use four-level cores with a straightforward generalization of discrete rotational symmetry, called $\ensuremath{\omega}$-rotation invariance, to encode pairs of coupled qubits and universal two-qubit logical gates. We include quantum errors as a main source of decoherence, and show that symmetry makes logical operations particularly resilient to untimely anisotropic qubit rotations. We propose a scalable scheme for universal quantum computation where cores play the role of quantum-computational transistors, or quansistors for short. Initialization and readout are achieved by tunnel-coupling the quansistor to leads. The external leads are explicitly considered and are assumed to be the other main source of decoherence. We show that quansistors can be dynamically decoupled from the leads by tuning their internal parameters, giving them the versatility required to act as controllable quantum memory units. With this dynamical decoupling, logical operations within quansistors are also symmetry-protected from unbiased noise in their parameters. We identify technologies that could implement $\ensuremath{\omega}$-rotation invariance. Many of our results can be generalized to higher-level $\ensuremath{\omega}$-rotation-invariant systems, or adapted to clusters with other symmetries.

Optoelectronic Resistive Memory Based on Lead‐Free Cs2AgBiBr6 Double Perovskite for Artificial Self‐Storage Visual Sensors

AbstractMimicking the human visual memory system has attractive prospects in the field of artificial vision. However, the prominent challenge of realizing human visual memory is how to detect and store image information at the same time, which demands a multifunctional electronic device that can sense and memorize image information like the brain. In this work, simple two‐terminal optoelectronic resistive random access memory (ORRAM) devices are demonstrated based on lead‐free Cs2AgBiBr6 perovskite, exhibiting a unique optoelectronic resistive characteristic that can be reset by UV light illumination. A proof‐of‐concept artificial self‐storage visual system based on the ORRAM is constructed, which shows similar reinforcement learning and memory forgetting functions to the human visual memory system, and realizes the integrated functions of image sensing and memory for a long‐term retention time (>6000 s). Theoretical calculations indicate that UV light illumination will induce the annihilation of Br defects and cause the fracture of conductive filaments, resulting in the optical RESET phenomenon. Furthermore, by integrating with perovskite solar cells, an all‐optically controlled universal implication logic gate is constructed. This work provides an important step toward the mimicry of human visual memory and the multifunctional artificial visual integration of perception and storage.

Optimization of an all-optical three-input universal logic gate with an enhanced contrast ratio by exploiting a T-shaped photonic crystal waveguide.

Universal gates (NAND and NOR) are used for any electronic circuit that is affordable and straightforward to build all logic gates (LoG). In this work, the T-shaped 2D photonic crystal (PhC) is exploited to design a three-input universal LoG premised on the beam-interference principle. The design criteria of pitch (a), rod radius (r), and refractive index (n) are employed to obtain a high impact output. The methodologies of plane wave expansion and finite-difference time-domain are employed for examining the framework of universal LoG at 1550 nm wavelengths (λ). The suggested universal LoG design has a compact size of 8.4µm×4.8µm. Additionally, the structure yields a high contrast ratio (CR) of 20.37 dB for the NAND LoG and 28.45 dB for the NOR LoG, and maximum transmission efficiency of 50.6% and 70% for the NAND and NOR gates; correspondingly, the best and worst three-input NAND gate response times are 19.5 ps and 21.4 ps. Similarly, the response time of the three-input NOR gate is 26 ps. The proposed universal gate's primary goal is to offer a high CR and a compact structure while being compatible with any other logic gate.