Unity Gain Cutoff Frequency Research Articles

Impact of channel doping engineering on the high-frequency noise performance of junctionless In0.3Ga0.7As/GaAs FET: A numerical simulation study

Abstract In this paper, the channel doping engineering is proposed to improve the benchmarking parameters of the analog/radio frequency and the high frequency noise performance of the junctionless (JL)-In0.3Ga0.7As/GaAs device. The proposed structure is called shell doped of channel-JLFET (SDCh-JLFET). The sub-gate doped layer thickness (D) and middle of channel impurity concentration (Nmiddle) are considered as additional factors to improve the analog/radio frequency parameters and high frequency noise performance of device. The SDCh-JLFET with a channel length of 10 nm, D = 1 nm, and Nmiddle = 2 × 1017cm−3 showed the transconductance of Gmmax = 3mS/um, unity gain cut-off frequency of fT = 700 GHz, the minimum noise figure of Nfmin = 0.84 db and available associated gain of Gass = 28.5 db. The Gmmax, fT, Nfmin and Gass parameters of the SDCh-JLFET device are improved by 76%, 36%, 35% and 26%, respectively, compared to JL-In0.3Ga0.7As/GaAs device without shell doping (JLFET) but with similar dimensions. The SDCh-JLFET device proposed in this paper can be a reasonable candidate for analog/radio frequency applications and high frequency noise.

Improved RF and DC performance in AlGaN/GaN HEMT by P-type doping in GaN buffer for millimetre-wave applications

In this paper, the RF and DC performance of AlGaN/GaN HEMT having p-type doping in GaN buffer layer was analysed. Novelty of this work lies in the inclusion of P-type doping in GaN buffer of proposed GaN-HEMT. The result shows the significance of p-type doping at GaN buffer layer for enhancing the RF characteristics of the AlGaN/GaN HEMT. The use of p-type doping in GaN buffer layer increase the conduction band minima in the channel and thereby improving the transconductance of the device. The proposed HEMT achieves a peak transconductance of 330 mS/mm at VGS = −2 V and a maximum drain current of 850 mA/mm. The unity-gain cut-off frequency, small signal capacitance and conductance were also extracted to demonstrate its influence on RF performance. The proposed GaN HEMT has exhibited a unity current gain cut-off frequency of 45 GHz, which is 40% higher than that of conventional HEMT. The improved RF and DC performance of proposed HEMT makes it suitable for millimetre-wave applications.

Performance enhancement of field effect transistor without doping junctions using In0.3Ga0.7As/GaAs for analog/RF applications

Reduction of transconductance related to the junctionless silicon (JL-Si) transistor shows challenges to its performance for analog/radio frequency (RF) applications. An effective way to increase the transconductance of JL-Si device without reducing its performance is to use III–V semiconductor materials with a high carrier mobility/velocity instead of silicon. In the present study, the application of In[Formula: see text]Ga[Formula: see text]As/GaAs structures is proposed in order to enhance the transconductance of double gate JL (DG-JL) with channel length of 10 nm and body thickness of 5 nm. The importance of the thickness of In[Formula: see text]Ga[Formula: see text]As layer as well as the indium mole fraction on the electrical characteristics of the proposed device is shown in terms of the transconductance by a numerical simulator. By decreasing the thickness of the In[Formula: see text]Ga[Formula: see text]As layer down to 1 nm for a specified mole fraction of 0.3, a maximum transconductance of 1.7 mS/um was obtained. Comparing the results of JL-In[Formula: see text]Ga[Formula: see text]As/GaAs device with JL-GaAs, JL-In[Formula: see text]Ga[Formula: see text]As and JL-Si structures, an increase of 21%, 18% and 44% in transconductance, respectively, was found. Moreover, simulation results show that the proposed structure exhibits output resistance of 300 G[Formula: see text], intrinsic gain of 32.5 dB and unity gain cut-off frequency of 513 GHz. Thus, the JL-In[Formula: see text]Ga[Formula: see text]As/GaAs device can be a good candidate for analog/RF applications.

Design and analysis of 10 nm T-gate enhancement-mode MOS-HEMT for high power microwave applications

Abstract In this work, we propose a novel enhancement-mode GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 10 nm T-gate length and a high-k TiO2 gate dielectric. The DC and RF characteristics of the proposed GaN MOS-HEMT structure are analyzed by using a TCAD Software. The device features are heavily doped (n++ GaN) source/drain regions for reducing the contact resistances and gate capacitances, which uplift the microwave characteristics of the MOS-HEMT. The enhancement-mode GaN MOS-HEMTs showed an outstanding performance with a threshold voltage of 1.07 V, maximum extrinsic transconductance of 1438 mS/mm, saturation current at VGS = 2 V of 1.5 A/mm, maximum current of 2.55 A/mm, unity-gain cut-off frequency of 524 GHz, and with a record maximum oscillation frequency of 758 GHz. The power performance characterized at 10 GHz to give an output power of 29.6 dBm, a power gain of 24.2 dB, and a power-added efficiency of 43.1%. Undoubtedly, these results place the device at the forefront for high power and millimeter wave applications.

Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications

In this paper, we investigated the performance of a dopingless (DL) double gate fieldeffect transistor (DL-DGFET) for ultra-low power (ULP) analog/RF applications. It is observed that the source/drain metal electrode work-function engineering in DL-DGFET yields improved analog/RF performance as compared to underlap inversion mode (IM) and junctionless (JL) DGFETs. The DL-DGFET exhibits superior electrostatic control, low threshold voltage variability, simpler fabrication process, and comparable ON state current as compared to IM- and JL-DGFETs. In addition, the DL-DGFET alleviates the inherent contradictory trade-off between gain and bandwidth by exhibiting the simultaneous improvement in intrinsic voltage gain (A vo ) and unity gain cutoff frequency (f T ). The well calibrated TCAD simulation results of the DL-DGFET show a minimum noise figure (NF min ) 1.27 times and 2.29 times less than the IM and JL-DGFET. At gate overdrive voltage of 0.1 V, the DL-DGFET achieves 5.08 times f T and 5.86 times maximum oscillation frequency (f MAX ) along with 3.59 times A vo in comparison to JL-DGFET. From simulation results, it is evident that the dopingless FET is a promising candidate for ultra-low power applications of analog and radio frequency (RF) domains.

Analysis of Wide-Bandgap Material OPFET UV Detectors for High Dynamic Range Imaging and Communication Applications

The ultraviolet (UV) photoresponses of Wurtzite GaN, ZnO, and 6H-SiC-based Optical Field Effect Transistor (OPFET) detectors are estimated with an in-depth analysis of the same considering the generalized model and the front-illuminated model for high resolution imaging and UV communication applications. The gate materials considered for the proposed study are gold (Au) and Indium-Tin-Oxide (ITO) for GaN, Au for SiC, and Au and silver dioxide (AgO2) for ZnO. The results indicate significant improvement in the Linear Dynamic Range (LDR) over the previously investigated GaN OPFET (buried-gate, front-illuminated and generalized) models with Au gate. The generalized model has superior dynamic range than the front-illuminated model. In terms of responsivity, all the models including buried-gate OPFET exhibit high and comparable photoresponses. Buried-gate devices on the whole, exhibit faster response than the surface gate models except in the AgO2-ZnO generalized OPFET model wherein the switching time is the lowest. The generalized model enables faster switching than the front-illuminated model. The switching times in all the cases are of the order of nanoseconds to picoseconds. The SiC generalized OPFET model shows the highest 3-dB bandwidths of 11.88 GHz, 36.2 GHz, and 364 GHz, and modest unity-gain cut-off frequencies of 4.62 GHz, 8.71 GHz, and 5.71 GHz at the optical power densities of 0.575 μW/cm2, 0.575 mW/cm2, and 0.575 W/cm2 respectively. These are in overall, the highest detection-cum-amplifi-cation bandwidths among all the investigated devices. The same device exhibits the highest LDR of 73.3 dB. The device performance is superior to most of the other existing detectors along with comparable LDR, thus, emerging as a high performance photodetector for imaging and communication applications. All the detectors show considerably high detectivities owing to the high responsivity values. The results have been analyzed by the photovoltaic and the photoconductive effects, and the series resistance effects and will aid in conducting further research. The results are in line with the experiments and the commercially available software simulations. The devices will greatly contribute towards single photon counting, high resolution imaging, and UV communication applications.

Assessment of THz Performance for a Lateral SiGe HBT on SOI With a Laterally Graded Base

This paper presents a simulation-based assessment of the design, characteristics, and feasibility of a lateral SiGe heterojunction bipolar transistor with a graded base on a silicon on insulator. A device was created with a focus on integration with the CMOS process, THz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , and low-power dissipation. These characteristics are achieved with an ultrathin base width of 22 nm, grading of the base, and modification of standard doping profiles. In TCAD simulations, the n-p-n device has a unity gain cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 1.2 THz and maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 2 THz. The p-n-p of the same design has f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 900 GHz and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 1.8 THz. Additional Monte Carlo plots that show electron velocity and carrier densities across the length of the device, and a discussion on ballistic effects in the proposed devices are presented. To demonstrate the feasibility of the device, a possible process flow for fabrication is also summarized.

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.

Tunable work function in Junctionless Tunnel FETs for performance enhancement

ABSTRACTThis paper explores the performance of a Junctionless Tunnel field effect transistor (JLTFET) by varying the work function (WF) of the gate electrodes. JLTFET exploits the working principle of a Tunnel field effect transistor (TFET) in Junctionless FETs (JLFETs) by tuning the WF of the two gates, control gate (CG) and auxiliary gate (AG). High Ion/Ioff ratio of 5.8 × 1011 and average subthreshold swing of 60 mV/decade are obtained for an optimised WF of CG and AG. DC parameters, threshold voltage (VT) and subthreshold swing (SS), AC parameters, intrinsic gain and unity gain cut-off frequency (ft) are extracted with respect to WF variation of the two gates. The JLTFET exhibits less SS and high intrinsic gain for higher values of WF of AG.

Polarization dependent charge control model for microwave performance assessment of AlGaN/GaN/AlGaN double heterostructure HEMTs

An accurate polarization dependent charge control-based analytical model is proposed for microwave performance assessment of $$\hbox {Al}_{0.15}\hbox {Ga}_{0.85}\hbox {N/GaN/Al}_{0.15}\hbox {Ga}_{0.85}\hbox {N}$$ double heterostructure high electron mobility transistors (DH-HEMTs) in terms of current, transconductance, gate capacitances and cutoff frequency. An analytical expression correlating the sheet carrier concentration in the two 2DEGs formed at the upper and lower heterointerfaces of a DH-HEMT is obtained. AlGaN/GaN/AlGaN DH-HEMTs are found to exhibit superior RF performance as compared to its single heterostructure counterpart in terms of higher drain current, improved transconductance, higher gate capacitance and higher unity-gain cutoff frequency. This improvement in the DH-HEMT is mainly attributed to the formation of two 2DEGs (at top and the bottom heterointerface) as compared to the single 2DEG in a SH-HEMT. The variation of drain current with drain voltage and with gate voltage of AlGaN/GaN SH-HEMTs and AlGaN/GaN/AlGaN DH-HEMTs is obtained analytically and found to agree reasonably well with that obtained using ATLAS 2D device simulation, thereby validating the proposed model.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement * * Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (ION) of about 0.2 mA and less leakage current (IOFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (gm), higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher fmax of 985 GHz is obtained for drain doping of 5 × 1017 cm−3 because of the reduced gate-drain capacitance (Cgd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of Cgd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values.

Studies of buried oxide properties on nanoscale GeOI pMOSFETs for design of a high performance common source amplifier

Using well-calibrated TCAD simulation we explore, for the first time, the impact of buried oxide (BOX) thickness and dielectric constant on the analog circuit performance of 30-nm ultra-thin body germanium-on-insulator (GeOI) pMOSFETs. Our findings show that GeOI MOSFETs with a 20 nm SiO2 BOX offer lower subthreshold leakage current, high transconductance, improved transconductance generation factor and high intrinsic voltage gain. Furthermore, while GeOI MOSFETs with a 20 nm thin HfO2 BOX exhibit the lowest output conductance and highest voltage gain, GeOI MOSFETs with a 200 nm thick HfO2 BOX yield the highest transconductance and unity gain cut-off frequency. Moreover, we design common source amplifiers using GeOI pMOSFETs, analyze and optimize their performance. Our results show that the highest amplifier gain of 6.18 and gain bandwidth of 15.32 GHz are obtained with 20 nm HfO2 BOX while the highest bandwidth of 3.85 GHz is achieved at BOX thickness of 200 nm.

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.

RF performance enhancement in multi-fin TFETs by scaling inter fin separation

This paper deals with the extraction of RF metrics of multi-fin Tunnel FET (TFET) with the inter fin separation (IFS) scaled up to 1nm. The structure of multi-fin TFET is designed by varying the number of fins (N) from 1 to 5. As the number of fins increases, the drive current (ID) gets multiplied and the maximum ID of 76µA can be achieved for N = 5. Higher ID is obtained without compromising the leakage current (IOFF) which is in the range of femto amperes. For the various values of IFS, RF metrics such as intrinsic gain (A0), unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), and admittance (Y) parameters are extracted for multi-fin TFETs. The results show for lesser values of IFS, higher intrinsic gain is obtained and the value does not affect as N increases. The maximum value of ft and fmax is obtained because of the electrostatic coupling between the two adjacent fins. The Y parameters are extracted at an operating frequency of 10GHz. It can be seen that Y parameters offer better values as the number of fins and IFS increases. This is due to the larger value of gate to drain capacitance (Cgd) which occurs because of the parasitic effect for higher values of IFS.

Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs

In this paper, the effect of eccentricity on Junction-based Silicon Nanowire FET, Junction-based Silicon Nanotube FET, Junctionless-based Silicon Nanowire FET, and Junctionless-based Silicon Nanotube FET is investigated. Three kinds of eccentric structures are considered here. The impact of eccentricity on effective gate oxide thickness thereby gate oxide capacitance, and effective channel width are studied using 3D numerical simulations. Average radius of an ellipse is used to generate a model which captures the impact of eccentricity on gate oxide capacitance, and verified using TCAD simulations in MOS nanowire structure. The impact of eccentricity on ON current (ION), OFF current (IOFF), ION/IOFF ratio, and Unity gain cutoff frequency are investigated. Eccentricity increases the effective gate oxide thickness, the effective channel width, ION, and IOFF but reduces ION/IOFF ratio.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

Investigation of electrostatic performance for a conical surrounding gate MOSFET with linearly modulated work-function

In this paper, for the first time a continuous variation of work-function based gate metal has been introduced in conical surrounding gate MOSFET. Here, a comparative study of the electrostatic as well as RF characteristics for basic conical surrounding gate MOSFET and the work-function modulated conical MOSFET is carried out using TCAD device simulator. These simulated results reveal that the work-function modulated conical model provides better electrostatic and RF performance in terms of drain current, transconductance, transconductance generation factor, unity gain cut-off frequency and intrinsic delay. An overall performance investigation has been presented for both the aforementioned models and verified using TCAD device simulator from Synopsys.

Analog and RF performance of a multigate FinFET at nano scale

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate-all-around devices

This paper deals with the effect of structural, doping, and work function parameter variations on the Radio-Frequency metrics, unity gain cutoff frequency (ft), non-quasi static delay, intrinsic gain, and noise figure in double-gate Fin Field Effect Transistor (FinFET), junctionless FinFETs, and conventional and junctionless gate-all-around devices using Technology Computer-Aided Design simulations. This is done quantitatively by performing a simple sensitivity study experiment and screening analysis through Plackett-Burman's design of experiment approach. The individual and overall rankings of the input parameters for the devices considered are given. Gate length affects FinFETs significantly, whereas it does not affect junctionless devices. The impact of work function on the output responses is more in junctionless devices compared with that of FinFET and gate-all-around devices. Ovality in gate-all-around devices has no impact on all the output responses.

Study of process induced variability of germanium-pTFET in analog and RF domain

Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. In this brief, we have investigated the two main process induced variability a) the thickness of the germanium body b) the thickness of gate oxide in Ge-pTFET using Sentaurus TCAD device simulation. The analysis is performed in complete analog domain along with the study of intrinsic RF performance parameters using small signal equivalent model with non-quasi static effect of the device under consideration. The process induced variability is estimated on the figure of merits (FOMs) such as drain current (Ids), transconductance (gm), output resistance (Ro), intrinsic gain (gmRo), unity-gain cutoff frequency (fT), transit frequency of maximum available power gain (fMAX), transport delay (τm), intrinsic resistance (Rgd) and intrinsic capacitances (Cgs, Cgd).