Unit Capacitor Research Articles

High Quality Factor Miniaturized CMOS Transmission Lines Using Cascaded T-Networks for 60 GHz Millimeter Wave Applications

This work presents an on-chip 60 GHz lumped element transmission line (TL) using cascaded T-networks with a high Quality factor. Each T-network consists of a series inductance with a shunt capacitance at its center. We have derived the design equations for this TL configuration and proved that a TL whose electrical length ≥ 60° achieves additional miniaturization when implemented with three or more cascaded T-networks. The inductance is implemented using a straight wire model with no ground below it, while the capacitance is implemented using a parallel plate model with a grounding pedestal. Both configurations guarantee maximum inductance per unit length and capacitance per unit area to further improve the miniaturization level. A quarter wavelength TL with three cascaded T-networks is fabricated as proof of concept. The measured and simulated results of the fabricated TL have good agreement, and the measured quality factor is 17 at 60 GHz.

Анализ влияния отклонений на нелинейность в гибридном RC-ЦАП

This paper is dedicated to the analysis of the effect of elements mismatch on the nonlinearity of N-bit hybrid segmented RC-digital-to-analog converter. In the structure of the hybrid digital-to-analog converter under consideration, a binary capacitive segment processes the most significant bits, whereas a unary resistive segment processes the least significant bits. Since the consi¬dered digital-to-analog converter is heterogenous, the elements of both segments differ by the type (resistors or capacitors) and area. This causes an optimal ratio of segments resolutions to shift in respect to the total DAC area minimization. Therefore, the goal of the current research is to obtain an expression for optimal segments resolutions in dependance on the ratio of unit capacitor and resistor areas. For this purpose, a parametric mathematical model of the considered converter has been developed in MATLAB. The elements arrays of both segments are influenced by random errors. The simulation of differential and integral nonlinearities has been carried out, which demonstrated a lower contribution of the resistive segment on nonlinearity, in contrast to the capacitive one. Besides, the increment of a capacitive segment resolution improves the yield of both nonlinearities.

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones

A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hitek 0.18 μm process, the Fast Fourier Transform(FFT) simulation results for 4096 points show that the signal-to-noise distortion ratio (SNDR) of the ADC can reach 90.2 dB and the effective number of bits (ENOB) can reach 14.69 bit. The average power consumption is 2.507mW at a supply voltage of 5 V, and this holds significant significance for the long-term deep-sea detection capabilities of sonar systems.

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

Biomimetic nanofiber-iongel composites for flexible pressure sensors with broad range and ultra-high sensitivity

To achieve high-performance flexible pressure sensors, it is imperative to develop biomimetic devices that mimic the functional structure and sensing mechanism of human skin. Nevertheless, the creation of skin-like sensors with both ultra-high sensitivity and broad response range poses a formidable challenge. Drawing inspiration from the tactile sensing mechanisms and hierarchical structure of human skin, we engineered a nanofiber-iongel (NFIG) composite with internally graded stiffness characteristics and surface semi-embedded microstructures through the application of electrostatic spinning and droplet injection methods. The gel mimics the layered nanofiber structure of human skin, along with its ion-sensing mechanism, and comprises an ion gel infused with highly elastic PVDF-HFP nanofibers. This study explores the impact of Young's modulus and external pressure on unit capacitance, and it establishes a fiber-gel composite model to assess how the fibers influence sensor performance, encompassing ion fluxes, displacements, and alterations in electric potential. These findings reveal that the utilization of high-modulus materials enhances ion mobility, decreases the double electrical layer thickness, and augments pressure resistance. Based on these discoveries, we engineered the NFIG sensor, which exhibits ultra-high sensitivity (>10,000 kPa−1), a wide pressure range (∼1000 kPa), and exceptional stability (over 5000 cycles). Furthermore, this sensor is versatile, finding utility in a range of human monitoring contexts, array configurations, and even skateboard monitoring, thereby substantiating its promise in the fields of human-computer interaction and sports health.

Parameter Optimization Design of the Commutation Circuit of a Hybrid DC-Current-Limiting Circuit Breaker

Aimed at the optimization design of the parameters of the commutation circuit of a hybrid DC-current-limiting circuit breaker (HDCCLCB), a parameter selection model considering the short-time withstand of the thyristor and the volume of the commutation circuit is proposed by simplifying the object, and the commutation circuit parameters were preliminarily obtained. In order to verify the correctness of the method of selecting the commutation circuit parameters, the circuit simulation model of the HDCCLCB was built. The experimental platform was built, and the breaking experiment was completed under the fault condition with the current rising rate of 20 A/μs. The correctness of the simulation model and parameter design method was verified by comparing the circuit model simulation results with the experimental results. In order to further optimize the parameters of the commutation circuit, a mathematical model for optimization design was established. Taking the maximum critical breakdown voltage under unit capacitance energy as the objective function, the arcing time before commutating and the current-limiting inductance and capacitance are enumerated to obtain the optimized commutation circuit parameters. By comparing this result with the result of the preliminary design, the objective function is improved by 20.7%, laying a solid foundation for further research and the development of current-limiting circuit breakers for medium-voltage DC systems.

Power management algorithm for standalone operated renewable distribution generator with hybrid energy backup in microgrid

<p>In a micro grid system during standalone condition the system may not be stable and might not compensate the required load. Especially for renewable source integrated micro grid system grid disconnected condition is more critical as the renewable sources are unpredictable. The renewable distribution generator needs backup module for support to the loads during standalone condition. In this paper complete distribution network with multiple renewable sources which include PV plant, wind plant and fuel cell source is modeled with power management algorithm (PMA) in only photovoltaic (PV) plant. PMA controls the hybrid backup modules supporting the PV DG. The hybrid backup modules considered for the support are battery unit and super capacitor (SC) unit. The battery and SC units charge or discharge as per the PMA controller with respect to power generated by the PV source. The charge and discharge of these units are dependent on PV power, state of charge (SOC) of battery and SOC of SC. These three sources compensate the critical load connected in the micro grid. A comparative analysis is carried out with and without backup modules and PMA during grid islanding condition on the proposed distribution network. All graphical and parametric comparisons are done using MATLAB/ Simulink software with time domain plots generated by PowerGUI tool.</p>

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm². The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.

The design of [formula omitted]-ADC in MEMS gyro interface ASIC

This article aims at MEMS gyroscope fully differential (FD) sensing, small signal output characteristics, designs a FD third-order cascade of integrators with feedforward (CIFF) delta-sigma analog-to-digital converter (ΔΣ-ADC). Abandoning the local negative feedback in the general third-order CIFF to reduce the difficulty of layout design. And under the premise of ensuring accuracy and stability, discarding the path directly from the input to the quantizer to reduce the circuit area and the influence of harmonics on the signal-to-noise-distortion ratio (SNDR) caused by the input sampling. In order to reduce the mismatch of capacitors, the gain factor and feedforward factor are optimized, so that each factor only retains one decimal place, and all capacitors on the layout are composed of 0.2pF unit capacitors in parallel. The tape-out measurement results show that the SNDR of the ΔΣ-ADC chip is 50.13 dB in the bandwidth (BW) range of 1kHz to 11kHz, and the input signal amplitude range is 1 mV to 800 mV.

An energy-efficient switching scheme based on a splitting structure

An energy-efficient switching scheme is proposed for successive approximation register analog-to-digital converters (SAR ADCs). Benefiting from the method based on MSB splitting and LSB splitting capacitor arrays, the total capacitance of DAC is reduced by 87%. Based on the switching method of the proposed scheme, the CDACs feed energy back to the reference power supply during the switching process to reduce energy consumption. And the proposed scheme achieves 99.61% energy saving reduction over the conventional scheme. In addition, adopting the strategy of unilateral switching can greatly reduce the energy consumption of switching driving, and at the same time reduce the complexity of the control logic. Using the LSB splitting capacitive technique, C-2C scheme is adopted without reducing the unit capacitance, which effectively improves the error caused by capacitance mismatch. The strategy of group reset is adopted, and there is no energy consumption during the reset process. The simulation results show that the differential nonlinearity and integral nonlinearity are 0.335LSB and 0.397LSB, respectively.

A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 mm2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step.

On the dynamics of a sinking object in a bubbling gas–solid fluidized bed by a ball-type inertial measurement unit and electrical capacitance tomography

The motion and dynamics of large objects in bubbling gas–solid fluidized beds are complex, especially for objects with densities similar to those of the bed. In this study, a method combining a ball-type inertial measurement unit and electrical capacitance tomography was used to investigate the motion and dynamics of objects with different densities sinking in a bubbling fluidized bed. The results show that the object dynamics are highly correlated with the object density, gas velocity, bed density, and bubble size. In the vertical direction, the significance of the bubble effect was determined by the size ratio of the object to the bubbles. In the horizontal direction, subject to the combined action of the bubble region in the center and the high-density region near the wall. The proposed ball-type inertial measurement unit can serve as a low-cost, non-invasive tool to monitor the dynamics of objects immersed in bubbling fluidized bed. • Proposed a noninvasive method to monitor the object dynamics. • Combined the inertial measurement unit and electrical capacitance tomography. • Bubbles and bed densities act differently on objects of different densities. • Proposed a coefficient C b to determine the significancy of bubble effect. • Lighter objects fluctuate in the horizontal direction, heavier objects move outward.

A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme

A low-power 12-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a reversible VCM-based capacitor (RVC) switching scheme is presented in this paper. The switching power consumption of the proposed scheme is 95% and 62.3% lower than that of conventional and VCM-based capacitor switching schemes, respectively. The use of a segmented DAC structure reduces the size of the largest capacitor from 211 unit capacitors in the conventional capacitor array to 24 unit capacitors. This 75% reduction in the capacitor area decreases the settling time of the DAC capacitor network as well as requirements on the bandwidth and driving capability of the reference source VREF. An ADC prototype with an active area of 0.218 mm2is fabricated in 180-nm 1P6M CMOS process. With supply of 1.8 V and sampling rate of 10 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 58.9 dB and consumes power of 0.36 mW, yielding a figure of merit (FOM) of 59.8fJ/conversion-step.

A novel capacitor recombination calibration method applied to 18-bit SAR ADC

In this paper, a calibration method applied to Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is designed, especially applied to the capacitive array in resistive–capacitive combined SAR ADC. Conventionally, auxiliary Digital-to-Analog Converter (DAC) foreground calibration, dynamic element matching (DEM) or digital background calibration are widely used to enhance linearity of data converters. This paper proposes an off-line capacitor selection calibration method that uses an optimal sequence of unity elements for an overall improvement of Signal to Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), differential nonlinearity (DNL) and integral nonlinearity (INL). It is worth mentioning that the capacitor mismatch only needs to be calibrated after power on, this kind of foreground calibration will not increase the power consumption of ADC during the normal operation, while the background calibration will consume power consumption all the time. It is important that the calibration proposed is highly relied on a high resolution comparator. This paper provides a high resolution comparator design, the resolution of the comparator reaches 8.35 μV, which already satisfies the demand of a 18-bit differential SAR ADC. During the process of calibration, all capacitors are divided into unit capacitors, and then the capacitors are sorted, reorganized to form each bit. The calibration method is verified by simulating a 18-bit SAR ADC with 500 Monte-Carlo runs, the simulation results show that the average value of SFDR is enhanced by about 36 dB and the average value of SNDR is enhanced by about 27 dB. Therefore, the proposed method is simple and significantly improves the static and dynamic performance of the ADC without obvious additional hardware, and greatly saves area and power consumption. Finally, it is worth mentioning that in high-precision SAR ADCs design, especially above 16 bits, comparator noise and the voltage coefficient of capacitors are the main factors limiting ADC performance, which are not considered in this work.

Improvement of electrospark deposition technology of steel units for drilling rigs and mining equipment

Introduction. The development of modern equipment and technologies for geological exploration and mining processes raises the problem of ensuring the reliability and durability of mechanic units operating under the conditions of elevated temperatures and pressures in the presence of aggressive external environments. In this regard, there is a need to create functional coatings with unique physical, mechanical and operational properties.Aim. To improve the performance of electrospark coatings based on an analysis of a cause-andeffect diagram and a regression study of the technological modes of processing steel units of geological exploration equipment (on the example of hydraulic cylinder rods of drilling pumps).Materials and methods. To harden the steel surfaces of hydraulic equipment parts, the technology of electrospark deposition (ESD) was used on an IMES-1001 mechanized installation using carbide electrodes and various gas media. In order to identify causal relationships between the factors affecting the hardened surface and to establish the most important factors affecting the quality of the formed coating, the Ishikawa diagram method was used and a regression analysis was performed. The adhesion activity of the obtained coatings was assessed by atomic force microscopy on a Solver PRO scanning probe microscope in a semi-contact air scanning mode using NSG10probe sensors with a resonance frequency of 219 kHz and a radius of curvature of the probe tip of 10 nm. When determining the strength of the adhesive interaction of the probe and the surface at one point, the absolute error was 15 nN. Tribological tests were carried out on a 2070-СМТ-1 standard friction machine according to the “disk-shoe” scheme.Results. The obtained cause-and-effect diagram showed that the technological modes of an electrospark deposition installation comprise a determining factor affecting the quality of the formed layers and coatings. In order to identify those process parameters that had the greatest effect, a regression analysis was carried out. The capacitance of the unit capacitors was found to have the greatest impact on the adhesion force formed by the ESD coating. Therefore, in order to reduce the strength of the adhesive interaction of surfaces and, as a result, increase their wear resistance, it is necessary to increase the capacitance of capacitors while reducing the voltage and processing time when implementing the ESD technology. On the basis of tribological tests, it is concluded that the minimum wear rate of coatings can be obtained by alloying the steel surface in an oxygen environment with a carbide electrode based on tungsten carbide with additives of elements that form unlimited solid solutions with the surface material and perform the role of fluxes (Ni-Cr-B-Si).Conclusion. Due to strict requirements to the performance of metal surfaces of units that enter into frictional interaction during the implementation of mining and exploration processes, there is a need to improve existing technologies for creating functional (wear-resistant) coatings.

A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect

A 10-bit-resolution successive approximation ADC with 70-Ms/s conversion rate and with a new configuration for capacitive DAC is represented in this paper. In the DAC structure proposed in this paper, the capacitors that form the Sub-DAC are smaller than the capacitors of the Sub-DAC of the other structures; therefore, the occupied area and the average switching energy in the proposed structure are less than in the other split-array structures, and the proposed structure is less susceptible to parasitic capacitance. Compared to the conventional split-array structure, the total capacitance and Sub-DAC parasitic capacitance are reduced by 15.87% and 46.87%, respectively. Also, the coupling capacitor is a unit capacitor, which improves the capacitor matching in the DAC array furthermore.To design and simulate the proposed 10-bit converter, 180-nm CMOS technology is used. Results of simulation prove that at 70 MS/s operating frequency, with a power supply equal to 1.8 V, and at Nyquist input frequency, SNDR of the proposed converter is 58.26 dB, that means ENOB is 9.39 bit, and SFDR is 64.87 dB. Consequently, the ADC FOM is equal to 123.5 fJ/conversion-step. Also, ramp-test simulation proves that INL and DNL are 0.53/+0.63 LSB and −0.6/+0.6 LSB, respectively. The proposed design consumes 5.8 mw at 70 MS/s operating frequency.

A low power asynchronous column-parallel 10-bit analog to digital converter with a high input impedance

This paper proposes a low power 10-bit asynchronous fully-differential column analog to digital converter (ADC) with successive approximation (SAR) and charge redistribution in a 180 nm SoI technology. The ADC is designed for use in Spacepix-2 monolithic active pixel sensor. A novel folded architecture of internal capacitive digital to analog converter (CDAC) is proposed. The total capacitance of CDAC is 512 fF, with a single unit capacitor capacitance only 0.5 fF and a size of 2.5 × 1.4 μm2. The total input capacitance of the proposed column ADC is only 220 fF. Two columns of a pixel matrix share a single ADC to double layout width. The layout area is 120 × 923 μm2. The sample rate is 4 MSps with power consumption of 225 μW from 1.8 V power supply.