Field-effect Transistors Research Articles

Analytical Modeling of Cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and Impact of Insulator Pillar Radius on Analog/RF and Linearity Parameters for Low Power Circuit Application.

In the current scenario of semiconductor technologies, the researchers are investigating the cylindrical Silicon-on-Insulator Schottky Barrier (SOISB) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) due to its enhanced analog/RF parameters, high ION /IOFF ratio and reduced ambipolarity. This study presents an analytical model for the cylindrical SOISB MOSFET, specifically focusing on how to calculate surface potential, threshold voltage, and drain current. Further, the research explores how altering the radius of the concentric SiO2 insulator pillar impacts the MOSFETs performance in analog/RF circuit applications. The Silvaco 3D device simulator has been used for conducting the numerical simulations for a channel length of 22nm and a silicon radius of 5nm. The SiO2 insulator pillar radius has been varied from 1nm to 4nm and its effect on the device characteristics has been investigated. The results show improved changes in analog/RF parameters and linearity, providing valuable insights for advanced semiconductor technologies.

Highly sensitive investigation of sirolimus by development of an ion-sensitive field effect transistor based on NH2-MIL-53(Fe)

Highly sensitive investigation of sirolimus by development of an ion-sensitive field effect transistor based on NH2-MIL-53(Fe)

Epitaxial growth of nonlayered 2D MnTe nanosheets with thickness-tunable conduction for p-type field effect transistor and superior contact electrode

Epitaxial growth of nonlayered 2D MnTe nanosheets with thickness-tunable conduction for p-type field effect transistor and superior contact electrode

Composite and Nanocomposite Thin-film Structures Based on Chitosan Succinamide

Aim: Currently, developing composite and nanocomposite materials based on natural polymers is attracting the growing attention of scientists. In particular, chitosan succinamide, a modified biopolymer, has good biocompatibility, biodegradability, and electrical conductivity, allowing it to be used as a functional material for creating various electronic devices, including sensors for use in medicine and pharmaceuticals. Composite sensors based on chitosan deriva-tives have found application for the recognition and determination of enantiomers of tryptophan, tyrosine, naproxen, and propranolol in human urine and blood plasma in tablet forms of drugs without a preliminary active substance. Methods: This article discusses the studies on composite and nanocomposite thin-film structures based on chitosan succinamide obtained using various fillers, such as graphene oxide, single-walled carbon nanotubes, and carbon adsorbents. Result: The studies used cyclic voltammetry, electrochemical impedance spectroscopy, and atom-ic force microscopy. The results created field-effect transistors based on the films in question as the transport layer. Conclusion: The mobility of charge carriers was estimated, and the following values were ob-tained: μ(SCTS) = 0.173cm2/V·s; μ(SCTS-GO) = 0.509 cm2/V·s; μ(SCTS-CP) = 0.269 cm2/V·s; μ(SCTS-CB) = 0.351cm2/V·s; μ(SCTS-SWCNT) = 0.713 cm2/V·s.

Modeling of β-Ga2O3 based double gate drain extended junction less FET and its parameter extraction methodology

Abstract A static current model of β—Gallium Oxide (β-Ga2O3) based double gate drain extended junction less field effect transistor (DG-DeJLFET) is proposed. The model consists of two voltage-controlled current sources connected in series. One of the current sources accounts for the operation of the junction less field effect transistor whereas, the other takes care of the drift region current. The model is formulated by considering the mobility degradation caused by moderately elevated electric fields. A parameter extraction methodology for this model is also proposed by considering the dominance of certain parameters in the specific regions of operation. In general, the parameter extraction technique is based on the variation in the device current behavior at moderate electric fields. The proposed parameter extraction methodology is validated by comparing the results with the data obtained from the TCAD simulation.

2D WS2 monolayer preparation method and research progress in the field of optoelectronics.

Two-dimensional Transition Metal Dichalcogenides (2D TMDs) have garnered significant attention in the field of materials science due to their remarkable electronic and optoelectronic properties, including high carrier mobility and tunable band gaps. Despite the extensive research on various TMDs, there remains a notable gap in understanding the synthesis techniques and their implications for the practical application of monolayer tungsten disulfide (WS2) in optoelectronic devices. This gap is critical, as the successful integration of WS2 into commercial technologies hinges on the development of reliable synthesis methods that ensure high quality and uniformity of the material. In this study, we present a comprehensive overview of the synthesis techniques for monolayer WS2, focusing on mechanical stripping, Atomic Layer Deposition (ALD), and Chemical Vapor Deposition (CVD). We highlight the advantages of each method, such as the uniform growth achievable with ALD at low temperatures and the capability of CVD to produce large-area, high-quality monolayers. Additionally, we summarize the performance of WS2 in various electronic and optoelectronic applications, including field-effect transistors (FETs), photodetectors, and logic devices. Our findings indicate that with ongoing advancements in film uniformity, compatibility with existing semiconductor processes, and the long-term stability of WS2-based devices, there is a promising trajectory for the transition of 2D WS2 from laboratory research to practical applications. This work not only addresses the existing gaps in the literature but also underscores the potential of WS2 to significantly impact the future of optoelectronic technologies.&#xD.

Amplifying Electron-Donor Signal of the "Water Gate" Enabled Low Detection Ability of a Field-Effect Transistor-Based Humidity Sensor.

Low humidity detection down to the parts per million level is urgently demanded in various industrial applications. The hardly detected tiny electrical signal variations caused by a very small amount of water adsorption are one of the intrinsic reasons that restrain the detection limit of the humidity sensors. Herein, a carbon-based field-effect transistor (FET) humidity sensor utilizing adsorbed water as the dual function of a sensing gate and analyte was proposed. Owing to the electron donor property of the "water gate" that can serve as a negative voltage exerted on the dielectric layer, the electrical conductivity of the FET's channel can be significantly modulated, therefore realizing signal amplification. The proposed sensor presents a detection limit of lower than 1% RH. Besides, the fabricated sensors show good batch consistency (response deviation of 0.5%), repeatability, long-term stability, and acceptable hysteresis (6.3% relative humidity (RH)) in humidity detection. We hope that our work can offer a novel strategy for the application and integration of low humidity detection from the device aspect rather than sensing materials synthesis.

Integrating an Extended-Gate Field-Effect Transistor in Microfluidic Chips for Potentiometric Detection of Creatinine in Urine

Integrating an Extended-Gate Field-Effect Transistor in Microfluidic Chips for Potentiometric Detection of Creatinine in Urine

Scale effects in BEOL compatible ferroelectric field-effect transistor memories with random phase fluctuation

Scale effects in BEOL compatible ferroelectric field-effect transistor memories with random phase fluctuation

Effects of Bottom Channel Coverage Ratio on Leakage Current and Static Power Consumption of Vertically Stacked GAA Si NS FETs

Abstract The performance of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) field-effect transistors (FETs) is significantly impacted by the non-ideal characteristics of the bottom channel, primarily due to etching process limitations. These issues lead to variations in the coverage ratio of the bottom channel, which impacts key device characteristics like leakage current and static power consumption. In this study, we used experimentally calibrated 3-D device simulations to analyze the effects of varying bottom channel coverage ratios from 60% to 100% on the GAA Si NS n-/p-type FETs for sub-2-nm technology nodes. Our results reveal an inverse relationship between the coverage ratio and leakage current and static power consumption. Notably, n-/p-type devices at 60% bottom channel coverage ratio exhibiting leakage currents 75.6 and 102.7 times higher than those with 100% bottom channel coverage ratio. This increase is linked to substantial variations in the off-state conduction (18.5%, 75 meV for n-type FETs) and valance (15.3%, 57 meV for p-type FETs) band energies. An 80% bottom channel coverage ratio proves to be an effective compromise, reducing parasitic leakage while addressing manufacturing feasibility. However, achieving a 100% bottom channel coverage ratio remains a critical challenge, highlighting the need for further research on fabrication optimization.

Dual Ionic Signal Detection: Modulation of Surface Charge of Nanofluidic Iontronics by Dual-Split Gate Voltages.

Nanofluidic iontronics, including the field-effect ionic diode (FE-ID) and field-effect ionic transistor (FE-IT), represent emerging nanofluidic logic devices that have been employed in sensitive analyses. Making analyte recognitions in predefined nanofluidic devices has been verified to improve the sensitivity and selectivity using a single ionic signal, such as ionic current amplification, rectification, and Coulomb blockade. However, the detection of analytes in complex systems generally necessitates more diverse signals beyond just ionic currents. Here, we demonstrated that dual ionic signals, steady ionic switching ratio, and transient response time (ts) act as detection signals modulated by dual-split gate voltages along the nanochannel for the detection of charged analytes. With an increase in gate voltage, the switching ratio decreases in both FE-ID and FE-IT, whereas the response time exhibits an exponential increase specifically in the FE-ID. Moreover, the response time shows no significant correlation with the external transmembrane voltage in the FE-IT. These results contribute to the optimization of reconfigurable iontronics through gate voltage modulation, providing a theoretical foundation for multiple ionic signal detection.

Carboxymethyl Cellulose as a Sustainable Dielectric Material for Organic Field-Effect Transistors

Carboxymethyl Cellulose as a Sustainable Dielectric Material for Organic Field-Effect Transistors

Self-heating optimisation of nanosheet field effect transistor performance with physics-based calibrated simulation setup

Self-heating optimisation of nanosheet field effect transistor performance with physics-based calibrated simulation setup

Gate- and flux-tunable sin(2φ) Josephson element with planar-Ge junctions

Hybrid superconductor-semiconductor Josephson field-effect transistors (JoFETs) function as Josephson junctions with gate-tunable critical current. Additionally, they can feature a non-sinusoidal current-phase relation (CPR) containing multiple harmonics of the superconducting phase difference, a so-far underutilized property. Here we exploit this multi-harmonicity to create a Josephson circuit element with an almost perfectly π-periodic CPR, indicative of a largely dominant charge-4e supercurrent transport. We realize such a Josephson element, recently proposed as building block of a protected superconducting qubit, using a superconducting quantum interference device (SQUID) with low-inductance aluminum arms and two nominally identical JoFETs. The latter are fabricated from a SiGe/Ge/SiGe quantum-well heterostructure embedding a high-mobility two-dimensional hole gas. By carefully adjusting the JoFET gate voltages and finely tuning the magnetic flux through the SQUID close to half a flux quantum, we achieve a regime where the sin(2φ) component accounts for more than 95% of the total supercurrent. This result demonstrates a new promising route towards parity-protected superconducting qubits.

Reliability of high-performance monolayer MoS2 transistors on scaled high-κ HfO2

The successful integration of ultrathin high-κ insulators is essential for the advancement of ultra-scaled field-effect transistors (FETs) based on two-dimensional (2D) semiconductors in future technology nodes. However, defects within the high-κ stack or at the interfaces can significantly degrade the performance of these “interface-only” devices, raising questions regarding their long-term reliability. Here, we study the reliability of monolayer MoS2 FETs on ultra-thin high-κ HfO2. Interestingly, we observe a two-stage threshold voltage shift (ΔVTH) under positive bias temperature stress (PBTS) and hot carrier degradation (HCD). This two-stage ΔVTH is absent in devices fabricated on exfoliated hBN, suggesting that the donor state generation (negative ΔVTH) is induced by atomic-layer-deposition (ALD) processes in HfO2-based devices. Elastic Recoil Detection Analysis (ERDA) indicates that hydrogen, likely from the ALD precursor, is a probable cause, highlighting the need for ALD process refinement to improve 2D FET stability for CMOS compatibility.

Ultralow Power Cold-Fuse Memory Based on Metal-Oxide-CNT Structure.

One-time programmable (OTP) memory is an essential component in chips, which has extremely high security to protect the stored critical information from being altered. However, traditional OTP memory based on the thermal breakdown of the dielectric has a large programming current, which leads to high power consumption. Here, we report a gate tunneling-induced "cold" breakdown phenomenon in carbon nanotube (CNT) field-effect transistors, and based on this we construct a "cold" fuse (C-fuse) memory where applying a mild gate voltage can break down the CNT channel without damaging the gate dielectric. The C-fuse is intrinsically different from dielectric-breakdown OTP, and it exhibits extremely low programming current (10-12 A), a large high-low resistance ratio (>1011), and a long retention time (>10 years). As the first reported OTP memory based on low-dimensional nanomaterials, C-fuse memory exhibits excellent storage performance and good uniformity, demonstrating great potential in constructing next-generation secure storage circuits.

Protein Detection Based on Field-Effect Transistor Biosensors for Diagnosing Diseases.

Proteins have been one of the most important biomarkers for diagnosing diseases, and field-effect transistor (FET) biosensors possess high sensitivity; are label-free; and feature real-time detection, rapidity, and easy integration for protein detection. FET biosensors are mainly made up of FET parts, such as channel materials, and bio parts, such as receptors. This Tutorial provides an in-depth exploration of FET biosensors for protein detection from the composition perspective and discusses the commercialization of point-of-care diagnostics of proteins based on FET biosensors.

Step-necking growth of silicon nanowire channels for high performance field effect transistors

Ultrathin silicon nanowires (diameter <30 nm) with strong electrostatic control are ideal quasi-1D channel materials for high-performance field effect transistors, while a short channel is desirable to enhance driving current. Typically, the patterning of such delicate channels relies on high-precision lithography, which is not applicable for large area electronics. In this work, we demonstrate that ultrathin and short silicon nanowires channels can be created through a local-curvature-modulated catalytic growth, where a planar silicon nanowires is directed to jump over a crossing step. During the jumping dynamic, the leading droplet undergoes significant stretching, producing a short necking segment of <100 nm in length, with a reduced diameter from approximately 45 nm to <25 nm. Compared to the FETs with uniform silicon nanowire channels, our step-necked silicon nanowire FETs exhibit substantially enhanced on/off current ratio Ion/off > 8 × 107 and a sharper subthreshold swing of 70 mV/dec, thanks to a stronger gating effect in the middle channel and markedly improved electric contacts at the thicker source/drain ends. These findings mark the pioneering experimental demonstration of catalytic growth acting as a deterministic fabrication method for precisely crafting engineered FET channels, ideally fitting the requirements of high-performance large-area displays and sensors.

Ultranarrow Semiconductor WS2 Nanoribbon Field-Effect Transistors.

Semiconducting transition metal dichalcogenides (TMDs) have attracted significant attention for their potential to develop high-performance, energy-efficient, and nanoscale electronic devices. Despite notable advancements in scaling down the gate and channel length of TMD field-effect transistors (FETs), the fabrication of sub-30 nm narrow channels and devices with atomic-scale edge control still poses challenges. Here, we demonstrate a crystallography-controlled nanostructuring technique to fabricate ultranarrow tungsten disulfide (WS2) nanoribbons as small as sub-10 nm in width. The WS2 nanoribbon junctions having different widths display diodic current-voltage characteristics, providing a way to create and tune nanoscale device properties by controlling the size of the structures. The transport properties of the nanoribbon FETs are primarily governed by narrow channel effects, where the mobility in the narrow channels is limited by edge scattering. Our findings on nanoribbon devices hold potential for developing future-generation nanometer-scale van der Waals semiconductor-based devices and circuits.

Controllable synthesis of nonlayered high-κ Mn3O4 single-crystal thin films for 2D electronics

Two-dimensional (2D) materials have been identified as promising candidates for future electronic devices. However, high dielectric constant (κ) materials, which can be integrated with 2D semiconductors, are still rare. Here, we report a hydrate-assisted thinning chemical vapor deposition (CVD) technique to grow manganese oxide (Mn3O4) single crystal nanosheets, enabled by a strategy to minimize the substrate lattice mismatch and control the growth kinetics. The material demonstrated a dielectric constant up to 135, an equivalent oxide thickness (EOT) as low as 0.8 nm, and a breakdown field strength (Ebd) exceeding 10 MV/cm. MoS2 field-effect transistors (FETs) integrated with Mn3O4 thin films through mechanical stacking method operate under low voltages (<1 V), achieving a near 108 Ion/Ioff ratio and a subthreshold swing (SS) as low as 84 mV/dec. The MoS2 FET exhibit nearly zero hysteresis (<2 mV/MV cm⁻¹) and a low drain-induced barrier lowering (~20 mV/V). This work further expands the family of 2D high-κ dielectric materials and provides a feasible exploration for the epitaxial growth of single-crystal thin films of non-layered materials.