Field-effect Transistors Research Articles

Aptasensor based on rGO-AuNPs Field-Effect Transistor for Selective Detection of Escherichia coli in River Water

Aptasensor based on rGO-AuNPs Field-Effect Transistor for Selective Detection of Escherichia coli in River Water

Composite and Nanocomposite Thin-film Structures Based on Chitosan Succinamide

Aim: Currently, developing composite and nanocomposite materials based on natural polymers is attracting the growing attention of scientists. In particular, chitosan succinamide, a modified biopolymer, has good biocompatibility, biodegradability, and electrical conductivity, allowing it to be used as a functional material for creating various electronic devices, including sensors for use in medicine and pharmaceuticals. Composite sensors based on chitosan deriva-tives have found application for the recognition and determination of enantiomers of tryptophan, tyrosine, naproxen, and propranolol in human urine and blood plasma in tablet forms of drugs without a preliminary active substance. Methods: This article discusses the studies on composite and nanocomposite thin-film structures based on chitosan succinamide obtained using various fillers, such as graphene oxide, single-walled carbon nanotubes, and carbon adsorbents. Result: The studies used cyclic voltammetry, electrochemical impedance spectroscopy, and atom-ic force microscopy. The results created field-effect transistors based on the films in question as the transport layer. Conclusion: The mobility of charge carriers was estimated, and the following values were ob-tained: μ(SCTS) = 0.173cm2/V·s; μ(SCTS-GO) = 0.509 cm2/V·s; μ(SCTS-CP) = 0.269 cm2/V·s; μ(SCTS-CB) = 0.351cm2/V·s; μ(SCTS-SWCNT) = 0.713 cm2/V·s.

Using a crumpled graphene field-effect transistor for ultrasensitive SARS-CoV-2 detection via its papain-like protease

Using a crumpled graphene field-effect transistor for ultrasensitive SARS-CoV-2 detection via its papain-like protease

Percolation theory-based KMC simulation for scaled Fe-FET based multi-bit computing-in-memory with temperature compensation strategy

In this letter, we investigate the impact of percolation transport mechanisms on ferroelectric field effect transistor (FeFET) multi-value storage with kinetic Monte-Carlo (KMC) simulation considering aspect ratio and temperature dependencies. It is found that the portion of the ferroelectric polarization, which dominates the threshold voltage shift of the FeFET, increases when aspect ratio of device decreases. Moreover, randomness of percolation path formation and variations of equivalent conductance can be suppressed, indicating mitigation of device-to-device variations and enhancement of separation of individual states. Besides, to further investigate an amorphous channel promising in multi-bit applications, disorder effects in channel contribute to intrinsic percolation transport, coupling with multi-domain dynamics in Fe-layer, are studied by the high temperature characterization. On this basis, the KMC scheme is further modified to predict multi-value distribution from 300 K to 400 K. To tackle such critical reliability issues induced inaccuracy for in-memory computing (CIM), an efficient write-verify scheme is proposed to mitigate state overlapping and provide in-depth insights for co-design of device reliability and multi-bit CIM performances.

Near-Infrared Phototransistor Using a SiGe-Based Light-Triggered Feedback Field-Effect Transistor with a Metasurface

Near-Infrared Phototransistor Using a SiGe-Based Light-Triggered Feedback Field-Effect Transistor with a Metasurface

Investigation of triple vertically stacked nanosheet FET with geometric variability at advanced technology node: DC, analog and RF performance benchmarking

Abstract This paper presents an in-depth analysis of the digital, analog, and radio frequency (RF) performance metrics of three-dimensional gate-all-around (GAA) triple nanosheet fieldeffect transistor (NSFET) designed for the 5 nm technology node. By optimizing the key physical dimensions of the NSFET specifically, a nanosheet width of 20 nm, thickness of 5 nm, and gate length of 12 nm, significant improvements in device performance were achieved. The optimized NSFET demonstrated a remarkable Ion/Ioff ratio of 2.99×10⁶, a low subthreshold swing of 65.63 mV/dec, and minimal drain-induced barrier lowering (DIBL) of 21.94 mV/V. Additionally, the device exhibited enhanced transconductance (gm = 3.2×10⁻⁴ S), contributing to a high intrinsic gain (Avo = 47 dB). In terms of RF performance, the NSFET achieved a cut-off frequency (fT) of 394 GHz and a maximum oscillation frequency (fmax) of 491 GHz, showcasing its potential for high-frequency applications. These results highlight the superior performance of NSFETs over FinFETs, making them a promising candidate for digital, analog, and RF circuit designs in advanced sub-5 nm technology nodes. The combination of excellent electrical characteristics and high-frequency performance positions NSFETs as a leading solution for next-generation integrated circuits.

Surface Doping of Mercury-Sensing Molecules in the Semiconducting Channel of Organic Field-Effect Transistors

Surface Doping of Mercury-Sensing Molecules in the Semiconducting Channel of Organic Field-Effect Transistors

Performance Evaluation and Optimization of Triple Cascode Operational Transconductance Amplifiers Using GNRFET Technology for Low Power Smart Devices

Abstract Abstract: Front-end circuits are crucial interfaces between digital electronics and real-world applications in Internet-of-Things (IoT) systems and portable smart devices, necessitating high-speed, energy-efficient, and compact designs. Advanced mixed-signal processing and actuation technologies are essential for leveraging the pivotal role of analog sensors in Artificial Intelligence (AI) functionalities. This study investigates emerging low-power nanoelectronics for analog circuit applications, focusing on Graphene Nano-ribbon Field-Effect Transistors (GNRFETs), particularly one-dimensional armchair graphene nanoribbons (AGNRs). Triple cascode operational transconductance amplifiers (TCOTAs) are implemented using GNRFETs and MOSFETs at the 32-nanometer technology node using HSPICE. Three distinct GNR-based TCOTA configurations are analyzed against conventional CMOS-based TCOTA to assess performance improvements. The evaluation highlights significant enhancements in GNR-based TCOTAs, particularly in the pure GNRFET-TCOTA variant, which exhibits a notable 33.8% increase in DC gain, a 21.4% improvement in common-mode rejection ratio (CMRR), and substantial growth rates of 5.85 and 8.47 times for slew rate and 3-dB bandwidth, respectively. Compared to Si-CMOS-based TCOTA, the pure GNR-based TCOTA demonstrates a 9.4% reduction in delay and an energy-delay product (EDP) approximately 4% lower. Insights into critical design parameters such as dimer lines (N), number of GNRs (nRib), and ribbon spacing (WSP) are provided, emphasizing their impact on circuit performance. This research underscores the potential of GNRFET to optimize operational transconductance amplifiers, enhancing analog circuit capabilities for IoT systems and portable electronics. The findings contribute to advancing nanoelectronics toward achieving higher performance and efficiency in future electronic applications.

Enhancing the RF performance at the Nanoscale using Double Gate Ferroelectric Field Effect Transistor

Abstract This work presents a proposed double-gate ferroelectric field-effect transistor with junctionless accumulation mode. Simulations with the TCAD Silvaco ATLAS simulator evaluate its characteristics regarding RF/analog needs for different channel lengths. The DG-FeFET configuration generates significant analog metrics, including transfer characteristics, output characteristics, transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA). Using the proposed structure, the parameters like gm, ION/IOFF, Av, and TGF have improved by more than 50%, 16-82%, 52.2%, and 50.83%, respectively. As a result, it has been discovered that, in comparison to junctionless accumulation mode ferroelectric FET (JAM-FE-FET) and junctionless ferroelectric FET (JL-FE-FET), the double gate ferroelectric FET (DG-FE-FET) topology enhances analog and RF performance. Because of this, the DG-FE-FET device shown here is an excellent choice for high-frequency systems.

A Novel Quaternary Half Subtractor Using 2:1 Multiplexer

Multiple-valued logic (MVL) is a logic in which there are more than two truth values. MVL is used due to difficulty in interconnection problems in binary system. Carbon nanotube field-effect transistors (CNTFET) is used to design the Quaternary Half Subtractor (QHS) circuit. Sub blocks of Module (0210), Module (1021), Module (2102), Module (3210) using three supply voltage devices and Quaternary Multiplexer 2:1 using pass transistor have designed in this paper. Therefore, compared to existing designs, less no. of transistors are needed. Comparing proposed Half subtractor using 4:1 MUX modules to current one’s reveals that the 2:1 multiplexer-based method leads in lower power usage. These proposed designs have proven to work satisfactorily under a variety of operating situations, including power, delay, and power delay product (PDP).

Analytical Modeling and TCAD simulation of Surface Potential and Drain Current for Pocket Doped Negative Capacitance Field-Effect Transistor

Abstract In this work, a 2D analytical model for a Highly Doped Double Pocket Double Gate NCFET (HDDP-DG-NCFET) device has been developed. The framework of the model is derived from the Poisson’s equation, LK equation and solved utilizing appropriate boundary conditions. The developed model is projected for several device variables, including electric field, surface potential and drain current.
Afterward, to verify the model’s accuracy, Sentaurus TCAD has been utilized for device simulation, and a good agreement with 85–95% precision is witnessed. The comprehensive and structured analysis of device is provided by examining variations in dimensions of device, ferroelectric material and oxide materials. The presented analysis shows that, the proposed HDDP-DG-NCFET device has significant potential for low power applications.

High-field electron transport and current saturation mechanism of open region channel in submicron split-gate AlGaN/GaN HFETs

Abstract Electron transport was studied at low and high electric fields, alongside current saturation mechanisms, within the open region channel of submicron split-gate AlGaN/GaN heterostructure field-effect transistors. By calculating the low-field electron mobility, it is found that the gate voltage-dependent polarization Coulomb field (PCF) scattering played a dominant role in the various scattering mechanisms. A coupled Technology Computer Aided Design (TCAD) and Monte Carlo (MC) simulation method was adopted in the analysis of the high-field electron transport. When the gate-source voltage is −4 V and the drain-source voltage is 10 V, the momentum relaxation effect caused by PCF scattering reduces the peak electron velocity in the open region channel from 3×107 cm/s to 1.2×107 cm/s. The presence of the virtual gate effect in the TCAD leads to a decrease in electron density within the open region channel, creating a localized high-resistance region and consequently a local high electric field. In this high-field region, electrons attain their saturation drift velocity, resulting in current saturation. Combining the virtual gate effect and the velocity-field relationship obtained by MC simulation, the simulation results of the output characteristics at VGS ≤ −4 V are in good agreement with the experimental results. This work extends the analysis of electron transport and PCF scattering theory in SG HFETs from low-field conditions to high-field conditions. The effect of the virtual gate effect on the channel current saturation in the open region is quantitatively revealed.

Modeling of β-Ga2O3 based double gate drain extended junction less FET and its parameter extraction methodology

Abstract A static current model of β—Gallium Oxide (β-Ga2O3) based double gate drain extended junction less field effect transistor (DG-DeJLFET) is proposed. The model consists of two voltage-controlled current sources connected in series. One of the current sources accounts for the operation of the junction less field effect transistor whereas, the other takes care of the drift region current. The model is formulated by considering the mobility degradation caused by moderately elevated electric fields. A parameter extraction methodology for this model is also proposed by considering the dominance of certain parameters in the specific regions of operation. In general, the parameter extraction technique is based on the variation in the device current behavior at moderate electric fields. The proposed parameter extraction methodology is validated by comparing the results with the data obtained from the TCAD simulation.

Integrating an Extended-Gate Field-Effect Transistor in Microfluidic Chips for Potentiometric Detection of Creatinine in Urine

Monitoring creatinine levels in urine helps to recognize kidney dysfunction. In this research, we developed a photocurable membrane for the detection of serum creatinine. Using a system based on field-effect transistors, we carried out creatinine quantification in synthetic urine. The device was able to cover values between 3 and 27 mmol L−1. The current sensitivity was 0.8529 (mA)1/2 mmol−1 L with 91.8% linearity, with the LOD and LOQ being 5.3 and 17.5 mmol L−1, respectively. The voltage sensitivity was 0.71 mV mmol−1 L with a linearity of 96.2%, with the LOD and LOQ being 4.2 and 14.0 mmol L−1, respectively. These data were obtained under flow conditions. The system performed very well during the measurements, with a hysteresis of about 1.1%. Up to 90 days after manufacture, the sensor still maintained more than 70% of its initial response. Even when used periodically during the first week and then stored unused at −18 °C, it was able to maintain 96.7% of its initial response. The device used in the flow setup only had a useful life of three days due to membrane saturation, which was not reversible. In the interference test, the membrane was also shown to respond to the urea molecule, but in a different response window, which allowed us to discriminate urea in synthetic urine. EGFETs can be used to identify variations in the creatinine concentration in urine and can help in therapeutic decision-making.

2D WS2 monolayer preparation method and research progress in the field of optoelectronics.

Two-dimensional Transition Metal Dichalcogenides (2D TMDs) have garnered significant attention in the field of materials science due to their remarkable electronic and optoelectronic properties, including high carrier mobility and tunable band gaps. Despite the extensive research on various TMDs, there remains a notable gap in understanding the synthesis techniques and their implications for the practical application of monolayer tungsten disulfide (WS2) in optoelectronic devices. This gap is critical, as the successful integration of WS2 into commercial technologies hinges on the development of reliable synthesis methods that ensure high quality and uniformity of the material. In this study, we present a comprehensive overview of the synthesis techniques for monolayer WS2, focusing on mechanical stripping, Atomic Layer Deposition (ALD), and Chemical Vapor Deposition (CVD). We highlight the advantages of each method, such as the uniform growth achievable with ALD at low temperatures and the capability of CVD to produce large-area, high-quality monolayers. Additionally, we summarize the performance of WS2 in various electronic and optoelectronic applications, including field-effect transistors (FETs), photodetectors, and logic devices. Our findings indicate that with ongoing advancements in film uniformity, compatibility with existing semiconductor processes, and the long-term stability of WS2-based devices, there is a promising trajectory for the transition of 2D WS2 from laboratory research to practical applications. This work not only addresses the existing gaps in the literature but also underscores the potential of WS2 to significantly impact the future of optoelectronic technologies.&#xD.

Amplifying Electron-Donor Signal of the "Water Gate" Enabled Low Detection Ability of a Field-Effect Transistor-Based Humidity Sensor.

Low humidity detection down to the parts per million level is urgently demanded in various industrial applications. The hardly detected tiny electrical signal variations caused by a very small amount of water adsorption are one of the intrinsic reasons that restrain the detection limit of the humidity sensors. Herein, a carbon-based field-effect transistor (FET) humidity sensor utilizing adsorbed water as the dual function of a sensing gate and analyte was proposed. Owing to the electron donor property of the "water gate" that can serve as a negative voltage exerted on the dielectric layer, the electrical conductivity of the FET's channel can be significantly modulated, therefore realizing signal amplification. The proposed sensor presents a detection limit of lower than 1% RH. Besides, the fabricated sensors show good batch consistency (response deviation of 0.5%), repeatability, long-term stability, and acceptable hysteresis (6.3% relative humidity (RH)) in humidity detection. We hope that our work can offer a novel strategy for the application and integration of low humidity detection from the device aspect rather than sensing materials synthesis.

Robust intrinsic quantum spin Hall states in transition metal M-doped graphene (M = Ti, Zr, Hf)

Abstract Graphene is a promising candidate for spintronics and low-dissipation quantum electronic device applications. However, its excessively weak spin-orbit coupling interaction (~ 24.0 μeV) makes the electric field modulation of spin currents almost impossible and the experimental observation of spin-polarized edge states in topological energy gap very challenging. These difficulties limit the practical applications of graphene. In this work, the electronic structures and topological properties of group IVB transition metal M-doped graphene (M = Ti, Zr, Hf) have been studied by first-principles calculations. Taking the Hf-doped graphene as an example, in the absence of spin-orbit coupling, this system possesses six equivalent Dirac points near the Fermi level in the Brillouin zone, owing to C 3z and inversion symmetries. These Dirac points exhibit linear dispersion in a wide energy range (about 1.00 eV), making this material a Dirac semimetal. When spin-orbit coupling interaction is considered, the Dirac points of this system are gapped with a spin-orbit gap of 16.4 meV, which is three orders of magnitude larger than that of graphene. Furthermore, the system is an intrinsic quantum spin Hall insulator with the nontrivial topological index Z 2 = 1. We also propose that the nontrivial topological properties are robust in a wide biaxial strain range from −5% to 5% and the spin-orbit gap further increases to 37.7 meV under 5% strain. Compared to the pristine graphene, our research has greatly enhanced spin-orbit coupling in this system with its nontrivial topological property preserved, which is crucial for the development of graphene-based spin field effect transistors. Moreover, such graphene-based robust topological material designs could also pave the way for a new generation of spintronics, ultra-low-dissipation electronics and quantum information processing devices.

Scale effects in BEOL compatible ferroelectric field-effect transistor memories with random phase fluctuation

Abstract In this study, we investigate the effects of dimensional scaling on device variation of back-end-of line (BEOL)- compatible ferroelectric field-effect transistor (FeFET) memory with amorphous oxide-semiconductor channel by considering random ferroelectric/dielectric (FE/DE) phase fluctuation. Our study based on TCAD simulation indicates that: i) For a given FE phase, scaling gate length not only improves memory window (MW) due to the sufficient ferroelectric switching during erase, but also increases MW variation (σMW), which is mainly dominated by high-voltage threshold (HVT) variation induced by erase operation. ii) For a given device size, reducing FE phase results in decreased MW with increased σMW. This σMW degradation could be suppressed at longer gate length due to the weak erase. iii) For gate width scaling, it has negligible effect on MW but induces the σMW increase, which could be ascribed to the increased probability of forming DE paths with larger grain-to-channel area ratio. Therefore, although scaling BEOL FeFET device size could increase MW, the increased σMW due to random FE/DE phase fluctuation may also need to be considered. These findings may provide insights for future FeFET design.

Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs

Abstract To improve the Ion/Ioff performance of transistors, it is crucial to significantly increase the charge carrier mobility in the channels of field-effect transistors. Tensile stress/strain is known to improve the electron mobility in the channels of nMOSFETs. This paper focuses on the STRASS (Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI) process for introducing tensile stress into the silicon channel of the next-generation n-type Fully Depleted Silicon-On-Insulator (FD-SOI) devices. This technique is challenging, especially for very thin silicon film channels (e.g., less than 10 nm), where the controlled creation of a buried amorphous layer by ion implantation is difficult. By carefully optimizing the individual process steps of the STRASS technique, we have achieved the transfer of up to 1.6 GPa of tensile stress into the silicon of blanket SOI wafers. Graphical abstract

Effects of Bottom Channel Coverage Ratio on Leakage Current and Static Power Consumption of Vertically Stacked GAA Si NS FETs

Abstract The performance of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) field-effect transistors (FETs) is significantly impacted by the non-ideal characteristics of the bottom channel, primarily due to etching process limitations. These issues lead to variations in the coverage ratio of the bottom channel, which impacts key device characteristics like leakage current and static power consumption. In this study, we used experimentally calibrated 3-D device simulations to analyze the effects of varying bottom channel coverage ratios from 60% to 100% on the GAA Si NS n-/p-type FETs for sub-2-nm technology nodes. Our results reveal an inverse relationship between the coverage ratio and leakage current and static power consumption. Notably, n-/p-type devices at 60% bottom channel coverage ratio exhibiting leakage currents 75.6 and 102.7 times higher than those with 100% bottom channel coverage ratio. This increase is linked to substantial variations in the off-state conduction (18.5%, 75 meV for n-type FETs) and valance (15.3%, 57 meV for p-type FETs) band energies. An 80% bottom channel coverage ratio proves to be an effective compromise, reducing parasitic leakage while addressing manufacturing feasibility. However, achieving a 100% bottom channel coverage ratio remains a critical challenge, highlighting the need for further research on fabrication optimization.