Undoped DG Research Articles

Compact modeling of the subthreshold characteristics of junctionless double-gate FETs including the source/drain extension regions

With the gate length shrinking to a few tens of nanometers, junctionless double-gate field-effect transistors (JL DG FETs) have become widely studied. In the subthreshold region, the electrical characteristics of JL DG FETs are sensitive to device parameters such as channel length, channel thickness, oxide thickness, doping concentration, and whether there are source/drain (S/D) extension regions or not. Therefore, it is essential for device engineers to develop compact models to run circuit simulations. In this paper, a compact JL DG FET model including S/D extension regions in the subthreshold region is proposed. Based on the superposition of the 1D Poisson equation and the 2D Laplace equation, the potential model is developed with and without S/D extension regions. Moreover, the subthreshold current, subthreshold slope, threshold voltage, and the drain induced barrier lowering are extracted without numerical iteration. The modeling results were verified with an ATLAS TCAD simulator and compared with a conventional undoped DG FET. We showed that the JL DG FET using the proposed compact model has better short-channel characteristics than the undoped DG FET with S/D extension regions, and we recommend that the doping concentration in the JL DG FET should be lighter for better subthreshold characteristics.

Symmetrical unified compact model of short-channel double-gate MOSFETs

An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

A neural computation to study the scaling capability of the undoped DG MOSFET

The DG MOSFET is one of the most promising candidates for further CMOS scaling beyond the year of 2010. It will be scaled down to various degrees upon a wide range of system/circuit requirements (such as high-performance, low standby power and low operating power). The key electrical parameter of the DG MOSFET is the subthreshold swing (S). In this paper, we present the applicability of the artificial neural network for the study of the scaling capability of the undoped DG MOSFET. The latter is based on the development of a semi-analytical model of the subthreshold swing (S) using the Finite Elements Method (FEM). Our results are discussed in order to draw some useful information about the ULSI technology.

A neural approach to study the scaling capability of the undoped Double-Gate and cylindrical Gate All Around MOSFETs

The Double-Gate and Gate All Around MOSFETs are two of the most promising candidates for the scaling of CMOS technology down to nanometer range. The excellent electrostatic control of the channel by the gate reduces dramatically short channel effects, such as charge sharing and DIBL. So, the objective of this work is to investigate and compare the scaling capability of the undoped DG and GAA MOSFETs using the artificial neural networks (ANNs). The optimization of this latter is based on the development of numerical models of subthreshold swing ( S) for short channel Double-Gate and Gate All Around MOSFETs under various modes of operation based on a two-dimensional analysis of electrostatics in the channel region by solving the two-dimensional Poisson equation with the mobile charge term included, and apply the physical insights gained from these models to investigate the impact of process variations on device characteristics. This study leads to the conclusion that cylindrical geometry is superior to the equivalent Double-Gate structure both in terms of the electrostatic control of the channel and the current ratio I on/ I off, indicating that the subthreshold slope is better controlled by the GAA MOSFET.

A Verilog-A model of an undoped symmetric dual-gate MOSFET

Abstract. We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.

A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism

We propose a design oriented charge-based model for undoped DG MOSFETs under symmetrical operation that aims at giving a comprehensive understanding of the device from the design strategy. In particular, we introduce useful normalizations for current and charges that in turn lead to very simple relationships among the physical quantities. Finally, we emphasize on the link that exists between this approach and the EKV formalism derived for bulk MOSFETs, which in turn leads to the unique g ms/ I D design methodology for DG architectures.

A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs

A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement.