Compact modeling of the subthreshold characteristics of junctionless double-gate FETs including the source/drain extension regions

Abstract

With the gate length shrinking to a few tens of nanometers, junctionless double-gate field-effect transistors (JL DG FETs) have become widely studied. In the subthreshold region, the electrical characteristics of JL DG FETs are sensitive to device parameters such as channel length, channel thickness, oxide thickness, doping concentration, and whether there are source/drain (S/D) extension regions or not. Therefore, it is essential for device engineers to develop compact models to run circuit simulations. In this paper, a compact JL DG FET model including S/D extension regions in the subthreshold region is proposed. Based on the superposition of the 1D Poisson equation and the 2D Laplace equation, the potential model is developed with and without S/D extension regions. Moreover, the subthreshold current, subthreshold slope, threshold voltage, and the drain induced barrier lowering are extracted without numerical iteration. The modeling results were verified with an ATLAS TCAD simulator and compared with a conventional undoped DG FET. We showed that the JL DG FET using the proposed compact model has better short-channel characteristics than the undoped DG FET with S/D extension regions, and we recommend that the doping concentration in the JL DG FET should be lighter for better subthreshold characteristics.