Under Unclamped Inductive Switching Research Articles

Observation of photoemission behaviour during avalanche breakdown of insulated gate bipolar transistor with defect in the metal contact

Under unclamped inductive switching (UIS) condition, there is non-uniformity in the intra-chip distribution of avalanche breakdown current in insulated gate bipolar transistors (IGBTs). The “current filaments”, which are concentrations of current caused by the parasitic PNP transistor, move through the chip and are thought to be related to failures. During the avalanche breakdown, the charge bremsstrahlung generates light over a wide wavelength range. We have previously reported that we constructed an observation system using a photomultiplier tube (PMT) and observed the avalanche breakdown photoemission with nanosecond time resolution. In this study, we used the same observation system to observe the photoemission behaviour of the samples in which the metal electrode was partially removed with a FIB (focused ion beam) to create a defective contact area. In the sample with the pseudo-defect, (a) there was an abnormal emission peak that did not correspond to the avalanche current change, (b) the randomness of the behaviour for each single pulse became extremely low, and (c) the pseudo-defect itself did not trap the current filament. These results may explain the tendency of IGBTs to have a higher probability of failure during repetitive avalanche breakdowns if they contain some defects.

Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability

The drift region of conventional drain extended NMOS (DeNMOSC) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOSC shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (Qg) and more than 65% in gate-to-drain coupling charge (Qgd). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (RON ×Qgd) and FoM2 (RON ×Qg) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (VBD/RON) and Baliga-FoM (VBD 2/RON) are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability.

Single-pulse observation of photoemission during avalanche breakdown in insulated gate bipolar transistor

Under unclamped inductive switching (UIS) condition, the distribution of avalanche breakdown current in insulated gate bipolar transistor (IGBT) is non-uniform. Many previous studies have shown the results of calculating current distribution and behavior using a device simulator. As a result of experimental observation, there are some reports that the temperature change of the device was observed by using infrared thermography. However, previous observational experiments had been conducted in only a few microseconds of time resolution. In order to understand the behavior of current concentration (filament) related to the breakdown of IGBTs, a method with a sub-microsecond time resolution and high sensitivity that can be observed even under single avalanche breakdown condition is required. In this study, we observed the photoemission associated with the avalanche breakdown current in IGBTs using a multi-anode photomultiplier tube (PMT) with a high temporal resolution of 20 ns. Since PMT can detect extremely weak light, it is possible to observe photoemission even under a single pulse bias condition. The increase and decrease and the movement of the light emitted from the current filament were observed. It was found that it changed every time the pulse was applied.

Investigation of the avalanche ruggedness of SiC MPS diodes under repetitive unclamped-inductive-switching stress

State of the art freewheeling diodes are connected antiparallel with a switch like IGBT or MOSFET and for latter also with the internal body diode. The diodes have to be rugged enough to overcome temporary overvoltage and overcurrent conditions during transient operation. SiC merged pin Schottky (MPS) diodes are one of the superior contenders and thus it is essential to make investigations under high avalanche energy. In this work, an avalanche ruggedness of 20 A/1.2 kV SiC MPS diodes was investigated far beyond the specified maximum ratings of the device under unclamped inductive switching (UIS) measurement. The function of avalanche energy versus applied inductance was investigated under single event avalanche stress. The reliability under high repetitive avalanche energy was studied in detail. A forward voltage drift, change in the Schottky junction voltage and increase in the leakage current was observed after the high repetitive avalanche stress far beyond the safe operating area. Detailed failure analysis was made, focusing on the degradation of the metallization and possible stacking faults (SFs) in the SiC bulk. Furthermore, the temperature was determined as a function of the blocking voltage during avalanche stress.

Avalanche Robustness of 4600 V SiC DMOSFETs

A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm2 SiC DMOSFETs under unclamped inductive switching (UIS) conditions is presented. Maximum single-pulse avalanche energies (EAS) as high as 1.07 J (13.75 J/cm2) and avalanche withstand times (tAV) as high as 71 μs are recorded. The variation of EAS and tAV with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including RDS,on, VTH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Different failure locations confined within the active area of the DMOSFETs are identified after avalanche failure for either low or high EAS failed devices and a tentative model to explain the failure physics is presented.

A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device

An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus, the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N+ source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.

Breakthrough performance, reliability and robustness of SiC Junction Transistors

ABSTRACT Despite having an npn epitaxial structure resembling a Si BJT, the switching performance of the SiC Junction Transistor or SJT is purely controlled by its terminal capacitances, similar to a SiC MOSFET or JFET. Further, the absence of a “high-resistance” SiC MOS channel in the SJT means that the SJT’s RON,sp is solely limited by the resistance of the n- drift region. Recently released SJTs feature RON,sp as low as 2 mΩ-cm2 for a breakdown voltage (BV) of 1600 V, and a RON,sp of 2.4 mΩ-cm2, for a breakdown voltage of 2000 V. Current gains > 100 are achieved, even on the highest current SJTs. Unlike Si BJTs, SJTs do not suffer from second breakdown, and can perform under unclamped inductive switching (UIS) conditions, even at full rated collector currents. Near-∞ Early voltage and a negative temperature co-efficient of current gain in a SJT ensure low collector currents under short-circuited load conditions, resulting in short-circuit withstand time as high as 14 µs, even at > 80% of the maximum rated BV. Recent technological developments have significantly improved the stability of the SJT current gain (β) under high-current stress conditions. A 1000-hour long, 200 A/cm2 DC current stress results in only 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. Similar β compression is observed, whether the collector current stress is applied at DC, or at a high switching frequency ≥ 200 kHz.

The Effect of Electrothermal Nonuniformities on Parallel Connected SiC Power Devices Under Unclamped and Clamped Inductive Switching

Nonuniformities in the electrothermal characteristics of parallel connected devices reduce overall reliability since power is not equally dissipated between the devices. Furthermore, a nonuniform rate of operational degradation induces electrothermal variations thereby accelerating the development of failure. This paper uses simulations and experiments to quantitatively and qualitatively investigate the impact of electrothermal variations on the reliability of parallel connected power devices under unclamped inductive switching (UIS) conditions. This is especially pertinent to SiC where small die areas mean devices are often connected in parallel for higher current capability. Measurements and simulations show that increasing the variation in the initial junction temperatures and switching rates between parallel connected devices under UIS reduces the total sustainable avalanche current by 10%. It is seen that the device with the lower junction temperature and lower switching rate fails. The measurements also show that the maximum sustainable avalanche energy for a given variation in junction temperature and switching rate increases with the avalanche duration, meaning that the effect of electrothermal variation is more critical with high power (high current and low inductor) UIS pulses compared with high energy (low current and high inductance) pulses. These results are important for condition monitoring and reliability analysis.

Evaluation of SiC MOSFET power modules under unclamped inductive switching test environment

High power commercial SiC MOSFET modules have been evaluated under unclamped inductive switching (UIS) environment from the point of view of judging their failure ruggedness. The power modules with 1.7kV/300A and 1.2kV/180A rating were stressed with avalanche currents of their rated current value. One SiC MOSFET module sustained its avalanche current value when tested at rated forward current condition (i.e., 180A) while the other power module failed during avalanche test even before reaching to its nominal rating current value (i.e., 300A) at 25°C. It is further shown that avalanche current of SiC-MOSFET modules is approximately insensitive of temperature variation under UIS behavior. A maximum avalanche energy of 2.43 and 3.23J was extracted when tested at maximum avalanche current of 165 and 220A for 1.7kV/300A and 1.2kV/180A rated power modules, respectively. These numbers far exceed than that of equivalent Si based IGBTs.

Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation Silicon Carbide (SiC) power MOSFETs under Unclamped Inductive Switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their ageing under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development.

Failure Analysis of Superjunction VDMOS Under UIS Condition

The failure mechanisms for two kinds of the 750-V Superjunction VDMOS (SJ-VDMOS) devices with different charge imbalance conditions (Qp <; Qn and Qp > Qn) under unclamped inductive switching (UIS) condition are investigated in detail by experiments and 2-D devices simulations in this paper. For Qp <; Qn, only the channel current appears in the device during the UIS turn-off process, and the avalanche current appears after the device turns off. Finally, the parasitic transistor of the device is triggered when the drain voltage reaches the BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , so the device fails. Unlike Qp <; Qn, the SJ-VDMOS device fails before its drain voltage reaches the BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> for the condition of Qp > Qn. Not only the channel current but also the avalanche current caused by ON-state breakdown appears during the UIS turn-off process until the gate voltage decreases below the threshold voltage in the SJ-VDMOS device. The avalanche current flows beneath the n+ region and leads to the activation of the parasitic transistor.

High Temperature Unclamped Inductive Switching Mode Evaluation of SiC JFET

Silicon carbide (SiC) unipolar transistors are an efficient choice in the design of high temperature 1200 V switching power supplies and dc-dc converters. To reduce the form factor and increase the power density of the circuit, the switching frequency must be high. This intensifies the negative impact of parasitic inductance and results in high voltage spikes that can drive a switching device into breakdown, followed by rapid destruction. To study the device performance under unclamped inductive switching (UIS) conditions, a normally-ON 1200 V/13-A SiC junction field-effect transistor (JFET) is driven into punch through breakdown using a single pulse. The testing is performed using an UIS setup, in which energy initially stored in an inductor is discharged through the JFET. The testing comprises of 90 single pulses each at 25 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C and 100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C case temperatures for different gate voltages and drain current values. The peak energy and power dissipated in the JFET are 621 mJ and 16 kW, respectively, at the rated 1200 V blocking voltage and 13-A drain current. The JFET triode breakdown characteristics are unchanged after 180 single-pulse switching events indicating the robust nature of the device under extreme breakdown conditions. In addition, the 621 mJ peak UIS energy and its corresponding 8871 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> density dissipated in the JFET are the highest reported for any SiC power device.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Optimization of nLDMOS Ruggedness under Unclamped Inductive Switching (UIS) Stress Conditions by Poly-Gate Extension

In this paper, the effect of poly-gate extension on improved ruggedness of n-type LDMOS is evaluated by two-dimensional (2D) device and circuit simulation. Multi-finger dimension of n-type LDMOS is subjected to Unclamped Inductive Switching (UIS) stress test to determine its ruggedness. It is shown that the poly-gate extended device yields approximately 15% higher avalanche energy handling capability (Emax) as compared to that without extended poly-gate region. This work suggests that the improvement in ruggedness of the optimized design is attributed to the suppression and shift of the electric field peaks away from the critical regions. The results from simulation are found to be in good correlation with experimental UIS test results in terms of avalanche energy range, identification of the mechanism of device-failure and hot-spot location. It is believed from the results obtained that this approach will have remarkable impact in the ruggedness if implemented for large-array devices (LAD).

High performance, FPGA-based test apparatus for unclamped inductive switching of IGBTs

A new concept for testing of power devices, in particular IGBTs, under unclamped inductive switching (UIS) conditions has been adopted and presented in this paper. The testing apparatus is completely FPGA-based and is capable of setting each time of the test (especially the protection one) with a precision of 20 ns. Furthermore, the FPGA embeds a microprocessor, which is responsible for the complete control of the apparatus by a personal computer. Fourth- and fifth-generation, low- and medium-voltage IGBTs have been tested thanks to the presented apparatus, and the collected results have been presented, evidencing significant behavioural differences between the two technologies.

Experimental Study on Improving Unclamped Inductive Switching Characteristics of the New Power Metal Oxide Semiconductor Field Effect Transistor Employing Deep Body Contact

A new power metal oxide semiconductor field effect transistor (MOSFET) with deep body contact (DBC), which improves the avalanche energy capability, is proposed and verified by experimental results. For the experiment, a 60 V, 1 A power MOSFET employing DBC has been fabricated using a complementary metal oxide semiconductor (CMOS) compatible deep Si trench process. Previous simulations show that DBC alters the direction of the current flow from the edge to the bottom of the p-body under unclamped inductive switching (UIS) conditions. DBC also suppresses the activation of the parasitic bipolar transistor due to the reduction of the current density beneath the n+ source. Experimental results show that the ruggedness of the proposed power MOSFET is improved without sacrificing any other electrical characteristics and increasing device area.

Electrothermal simulations in punchthrough and nonpunchthrough IGBT's

The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs.