Abstract
The drift region of conventional drain extended NMOS (DeNMOSC) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOSC shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (Qg) and more than 65% in gate-to-drain coupling charge (Qgd). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (RON ×Qgd) and FoM2 (RON ×Qg) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (VBD/RON) and Baliga-FoM (VBD 2/RON) are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability.
Highlights
Drain Extended MOSFET (DeMOS) is extensively used as a high voltage device in SoC and integrated circuit designs
We present a detailed investigation of the switching avalanche reliability of optimized Drain extended NMOS (DeNMOS) structures using electrothermal simulations to explain the time evolution of bipolar triggering, space charge modulation, and lattice heating
After LOV scaling, implementation of drift region optimization techniques resulted in the desired onstate safe operating area (SOA) and increased hot carrier stress (HCS) reliability
Summary
Drain Extended MOSFET (DeMOS) is extensively used as a high voltage device in SoC and integrated circuit designs. It finds application in interface and I/O circuit design due to its high voltage blocking capability and integration with advanced CMOS processes [1]-[4]. A power device gate charge (Qg) is an industry-standard metric. A low gate charge value gives high switching performance by reducing switching loss and delay. Multiple gate charge optimization techniques for lateral power MOSFETs are discussed earlier [5]-[10]. Schottky contact [9] and low-k dielectric in trench gate MOSFET [10] significantly improved the switching figure of merit and dynamic performance by reducing the gate charge
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