Unclamped Inductive Switching Test Research Articles

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plate junction electric field of 2.8 MV/cm, being close to the material limit for GaN. The device also shows a high on/off ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

Effect of Termination Region on Unclamped Inductive Switching Failure for 4H-SiC VDMOS

The effect of the termination structure on the unclamped inductive switching (UIS) failure is analyzed for two kinds of SiC MOSFET, where S-MOS and G-MOS termination structure are adopted. The MOSFETs are named as S-MOS and G-MOS according to the buses connecting with different electrodes in the termination region. The experimental results indicate that the avalanche energy G-MOS can withstand is 1.15 times larger than that of S-MOS. To understand what are the factors that lead to different UIS capabilities, further static measurements and hotpot mapping after UIS test are done, and technology computer aided design (TCAD) simulation also is done to further confirm the principle.

Investigation of the avalanche ruggedness of SiC JBS diodes with floating limiting rings under single unclamped-inductive-switching stress

In this paper, the single pulse avalanche robustness of SiC Junction Barrier Schottky (JBS) diode with different termination designs is investigated with simulations and experiments. Planar floating limiting rings (FLRs) and trench FLRs for the JBS diodes are designed and fabricated, and their avalanche current and energy capabilities are evaluated by unclamped inductive switching tests. The experiment and simulation indicate that a moderate first ring spacing window (S1) can achieve better device performance. Additionally, the single avalanche current stress measurements imply that the JBS diode with trench FLRs has better robustness and achieves better device reliability.

Analysis of Ruggedness of 4H-SiC Power MOSFETs with Various Doping Parameters

This work investigates the effect of the doping concentration of SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs) under an unclamped inductive switching (UIS) condition. Switching circuits such as inverters and motor-drive circuits often face unexpected operating conditions; therefore, a UIS test is performed to assess the avalanche ruggedness of the device, and design parameters such as the doping concentration should be considered to improve the UIS characteristics. Technology computer-aided design circuit simulation results, such as the current flows during failure and electrical changes, were obtained by changing the doping concentration of each region in the SiC power MOSFET.

Unclamped Inductive Switching Robustness of SiC Devices With Parallel-Connected Varistor

Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3–6 times higher for planar MOSFETs and 5–10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.

Application of N parallel-connected SiC MOSFETs to solid-state circuit breakers based on UIS tests

N parallel-connected SiC MOSFETs were investigated to apply to solid-state circuit breakers (SSCB), and it is an extension of a method that was proved valid by experiment of two parallel-connected SiC MOSFETs. The unclamped inductive switching (UIS) test was considered as the emergency interruption of SSCBs in this research. Because of the variations of breakdown voltage among SiC MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction prematurely. There are many compound cases for several SiC MOFETs with a certain maximum breakdown voltage variation. And the worst case, where the breakdown voltage of one device is assumed as the lowest, whereas the other devices have the same breakdown voltage, was extracted from the calculated results of four parallel-connected situation. In the worst case, it was found that the relation of breakdown voltage variations and current capacity is linear. Moreover, the distributions of breakdown voltage were taken as normal distributions. Using the worst case and distributions, a linear relation of breakdown voltage distributions and rated current of an SSCB could be concluded as a function of paralleled-connected numbers (N). Utilizing the function, the necessary breakdown voltage distributions and N of SiC MOSFETs can be evaluated for SSCBs meeting a certain yield ratio and current.

Over 10 kA/cm2 inductive current sustaining capability demonstrated in GaN-on-GaN pn junction with high ruggedness

This work presents specific investigation on the simultaneous demonstration of superior forward-current-sustaining and avalanche-breakdown-dissipating capability in GaN pn junction, which is critical for the ruggedness of future high-power-figure-of-merit vertical GaN MOSFET in tolerating inductive current strikes. Based on the doping profile design and edge electric field modulation in the pn junction, over 10 kA/cm2 current handling capability in both forward and reverse direction has been achieved. Meanwhile, no degradation in the device performance has been observed under continuous forward current stress tests and consecutively repetitive unclamped inductive switching tests, revealing the excellent ruggedness of state-of-art GaN-on-GaN pn junction against the inductive energy transients, thus promising reliable operation in the vertical power device applications.

Robustness of Cascode GaN HEMTs in Unclamped Inductive Switching

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and an Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , is still lacking. This article fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by avalanche in the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4–1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8–2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency dependent. At 100 kHz, the failure boundary (∼1.3 kV) is even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices show large but recoverable parametric shifts. All these failure and degradation behaviors can be explained by the buffer trapping in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.

SiC double-trench MOSFETs with source-recessed structure for enhanced ruggedness

A novel SiC double-trench MOSFET (DT-MOS) with source-recessed structure is proposed and investigated via Sentaurus TCAD simulations in this paper. The lateral resistance area beneath the source region is completely eliminated, thus suppressing the turn-on of the parasitic npn transistor effectively. As a result, the short-circuit withstanding time, the single pulse avalanche energy (E av) under unclamped inductive switching test and the threshold voltage for single-event burnout are improved by 28%, 14% and 67%, respectively, when compared to the traditional state-of-the-art SiC DT-MOS, indicating its great potential for harsh environment applications.

Investigations on acceptable breakdown voltage variation of parallel-connected SiC MOSFETs applied to olid-state circuit breakers

This paper aims to investigate the acceptable breakdown voltage variation of parallel-connected SiC power MOSFETs applied to solid-state circuit breakers (SSCB) under different total current conditions and its numerical simulation model. Due to variation of breakdown voltage among SiC power MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction. The unclamped inductive switching (UIS) test was imaged as the emergency interruption of SSCBs in this research. The UIS test of two parallel-connected SiC power MOSFETs was implemented. Proposed numerical simulation represents the experimental results with failure criteria by considering self-heating due to imbalanced current flowing. And it was found that the acceptable breakdown voltage variation and the total current have a linear relation.

Surge Current and Avalanche Ruggedness of 1.2-kV Vertical GaN p-n Diodes

This letter reports the avalanche and surge current ruggedness of the industry's first 1.2-kV-class vertical GaN p-n diodes fabricated on 100-mm GaN substrates. The 1.2-kV vertical GaN p-n diodes with a 1.39-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device area and an avalanche breakdown voltage of 1589 V show a critical avalanche energy density of 7.6 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in unclamped inductive switching tests, as well as a critical surge current of 54 A and a critical surge energy density of 180 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 10-ms surge current tests. All these values are the highest reported in vertical GaN devices and comparable to those of commercial SiC p-n diodes and merged p-n Schottky diodes. These GaN p-n diodes show significantly smaller reverse recovery compared to SiC p-n diodes, revealing less conductivity modulation in n-GaN. The negative temperature coefficient of differential on-resistance and the anticlockwise surge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> locus are believed to be due to the increased acceptor ionization in p-GaN and the decreased contact resistance at high temperatures. These results suggest a high ruggedness of GaN p-n junctions with small bipolar currents and fast switching capabilities. As the first electrothermal ruggedness data for industry's vertical GaN devices, these results provide key new insights for the development of vertical GaN devices as well as their application spaces.

New Failure Mechanism Induced by Current Limit for Superjunction MOSFET Under Single-Pulse UIS Stress

New failure mechanism induced by current limits has been investigated for the superjunction MOSFET (SJ-MOSFET) under single-pulse unclamped inductive switching (UIS) test stress. It is found that the local charge imbalance ( Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> > Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) at the chip corner produces a hotspot during the UIS test. The failure of the device induced by the hotspot depends on the magnitude of the avalanche current. For a low avalanche current, the avalanche current is redistributed from the local charge imbalance region to the charge balance region due to the lattice temperature increasing, resulting in the local heating toward the full-scale heating. However, for a high avalanche current, the negative differential resistance (NDR) effect plays a dominant role in the local charge imbalance region, decreasing the dynamic breakdown voltage (BV) sharply. Therefore, the hotspot is locked at the charge imbalance region; then, the device is destroyed in a short time. Finally, an SJ-MOSFET with more p-type charges at the chip corner is produced to improve the avalanche capability relating to the current limit, also verifying the mechanism analysis.

Investigation of acceptable breakdown voltage variation for parallel-connected SiC MOSFETs during unclamped inductive switching test

Current flowing through parallel-connected SiC MOSFETs are imbalanced during unclamped inductive switching (UIS) test, which can be imaged as the emergency interruption of solid-state circuit breakers, due to variations of breakdown voltage. The imbalanced current can drive devices into thermal destruction. This study evaluated acceptable breakdown voltage variations of two parallel-connected SiC MOSFETs under different total current, load inductances, and breakdown voltage temperature coefficient conditions during UIS mode operation by numerical simulation. The acceptable variation at 298 K was found to decrease with increasing total current and be influenced by the change of total current greater with larger inductances. SiC MOSFETs with larger breakdown voltage temperature coefficients allowing larger variations were also clarified.

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.

Trap-Mediated Avalanche in Large-Area 1.2 kV Vertical GaN p-n Diodes

This work studies the avalanche characteristics of the 1.2 kV vertical GaN p-n diodes with implanted edge termination, based on quasi-static current-voltage ( I-V ) sweeps and unclamped inductive switching (UIS) tests. The UIS tests reveal a ~1.7 kV avalanche breakdown voltage ( $BV_{{\text {AVA}}}{)}$ , 51 A maximum avalanche current ( ${I}_{{\text {AVA}}}{)}$ , and 63 mJ maximum avalanche energy ( ${E}_{{\text {AVA}}}$ ). The ${I}_{{\text {AVA}}}$ and ${E}_{{\text {AVA}}}$ are the highest reported in high-voltage GaN power devices. A lower $BV_{{\text {AVA}}}$ is observed in the I-V curves and a trap mediated avalanche model is proposed to explain it. The $BV_{{\text {AVA}}}$ in I-V curves is believed to be induced by avalanche-assisted trap-filling in the edge termination region, while the $BV_{{\text {AVA}}}$ in the UIS test reflects the robust avalanche at the main p-n junction. These results provide important new insights on the avalanche breakdown in GaN devices and address some seemingly contrary observations of vertical GaN p-n diodes published recently.

1200-V 4H-SiC Merged p-i-n Schottky Diodes With High Avalanche Capability

In this article, the avalanche capability of the 1.2-kV 4H-SiC junction barrier Schottky (JBS) and merged p-i-n Schottky (MPS) diodes is investigated through simulation and experiments. For MPS diodes, the width of the wide P+ region (W) is found to have great effects on the device avalanche capability. MPS diodes with varied W-values (3-20 μm) and JBS diode are designed and fabricated, and their avalanche energy/current capability is tested with unclamped inductive switching tests. The experimental results show that the MPS diode has an optimized avalanche capability at W = 8-μm design. Simulation study reveals that the avalanche current is mainly distributed at the edges of the P+ regions in the JBS/MPS diodes as a result of the curvature-effect-induced electric field crowding. The localized current crowding and unbalanced current distribution in the avalanche mode contribute to a reduced effective power dissipation area and a weaker avalanche capability. The current nonuniformity coefficient (k) is used to characterize the severity of the current unbalance, and it is found that kdeclines as Wincreases when W = 3-8 μm and then gets increased when W exceeds 8 μm. Both the experimental and simulation results indicate that the MPS diode is superior to the JBS diode in avalanche capability, and the width of the wide P+ region in the MPS diode has an optimal design (8 μm in this article) which corresponds to the alleviated current crowding issue and 9%-19% improvement of the avalanche capability.

Evaluation of SiC-MOSFET by Repetitive UIS Tests for Solid State Circuit Breaker

This paper investigates a degradation of SiC power device for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. Being much lower compared with Si devices, it has been considered an application for DC circuit breakers using SiC semiconductor. In order to use for the DCbreaker, it is essential to evaluate the destructive endurance for UIS test.This paper evaluates a deterioration phenomenon by paying attention to the decrease of the gate voltage of the SiC-MOSFETs under the degradation at repetitive UIS test.

Failure Mechanism of Avalanche Condition for 1200-V Double Trench SiC MOSFET

Due to superior properties of silicon carbide (SiC), the unipolar conduction mechanism of metal-oxide-semiconductor-field-effect transistor (MOSFET), and the structural feature, double trench SiC MOSFETs have great potential to be one of the next-generation power switches. In this article, an avalanche safe operation area (SOA) is established, and a new failure behavior of 1200-V double trench SiC MOSFET is revealed timely through unclamped inductive switching (UIS) test (300 K of initial temperature). With comprehensive analyses involving terminal impedance measurement, monitoring of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> before and after each avalanche test, inner electric field comparison by physics-based device modeling, maximum die temperature estimation, and decapsulation validation, the predominant failure mechanism (fracture of trench gate oxide) is identified for double trench SiC MOSFET under UIS test. Before the maximum die temperature approaches the melting point of source metal, the fracture of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer located at gate trench bottom and corner occurs, which is degraded by duration, excessive electric field, and elevated temperature. Accordingly, we propose I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> as a predicting indicator of avalanche failure, which should be a key monitoring scheme in particular for trench type SiC MOSFET.

Degradation characteristics of SiC power devices for DC circuit breaker by repetitive unclamped inductive switching test

This paper investigates the degradation of SiC power devices for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. The ON resistance of SiC power devices such as MOSFET and JFET are lower compared with Si devices. Therefore, SiC power devices are suitable for use as DC circuit breakers. Several papers have discussed degradation of SiC power devices; however, few studies have determined a suitable power device for a DC breaker from a degradation standpoint. In this paper, four types of SiC devices were subjected to repetitive UIS tests. Our research demonstrated SiC-JFET to be suitable for a DC breaker.