Thermometer Code Research Articles

Implementation of Power Efficient Flash Analogue-to-Digital Converter

An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

Visual Protection of HEVC Video by Selective Encryption of CABAC Binstrings

This paper presents one of the first methods allowing the protection of the newly emerging video codec HEVC (High Efficiency Video Coding). Visual protection is achieved through selective encryption (SE) of HEVC-CABAC binstrings in a format compliant manner. The SE approach developed for HEVC is different from that of H.264/AVC in several aspects. Truncated rice code is introduced for binarization of quantized transform coefficients (QTCs) instead of truncated unary code. The encryption space (ES) of binstrings of truncated rice codes is not always dyadic and cannot be represented by an integer number of bits. Hence they cannot be concatenated together to create plaintext for the CFB (Cipher Feedback) mode of AES, which is a self-synchronizing stream cipher for so-called AES-CFB. Another challenge for SE in HEVC concerns the introduction of context, which is adaptive to QTC. This work presents a thorough investigation of HEVC-CABAC from an encryption standpoint. An algorithm is devised for conversion of non-dyadic ES to dyadic, which can be concatenated to form plaintext for AES-CFB. For selectively encrypted binstrings, the context of truncated rice code for binarization of future syntax elements is guaranteed to remain unchanged. Hence the encrypted bitstream is format-compliant and has exactly the same bit-rate. The proposed technique requires very little processing power and is ideal for playback on hand held devices. The proposed scheme is acceptable for DRM of a wide range of applications, since it protects the contour and motion information, along with texture. Several benchmark video sequences of different resolutions and diverse contents were used for experimental evaluation of the proposed algorithm. A detailed security analysis of the proposed scheme verified the validity of the proposed encryption scheme for content protection in a wide range of applications.

Algebraic Modeling of New Enhanced Linearity Threshold Comparator based Flash ADC

This paper describes flash ADC design using linearity improved threshold quantized comparator. Here, the need for a reference voltage generation network has been eliminated in a 4 bit flash ADC; with completely digital cell based comparators. Output generated from comparator called thermometer code is related mathematically with binary conversion. This conversion property is used for mathematical modeling and complexity reduction of decoder circuitry by semi-parallel structuring of comparators. Circuit is designed in 250nm technology and it exhibits satisfactory performance even in temperature and process variation.

A New RNS based DA Approach for Inner Product Computation

This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{n}$</tex> </formula> modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.

Continuous real-world inputs can open up alternative accelerator designs

Motivated by energy constraints, future heterogeneous multi-cores may contain a variety of accelerators, each targeting a subset of the application spectrum. Beyond energy, the growing number of faults steers accelerator research towards fault-tolerant accelerators. In this article, we investigate a fault-tolerant and energy-efficient accelerator for signal processing applications. We depart from traditional designs by introducing an accelerator which relies on unary coding , a concept which is well adapted to the continuous real-world inputs of signal processing applications. Unary coding enables a number of atypical micro-architecture choices which bring down area cost and energy; moreover, unary coding provides graceful output degradation as the amount of transient faults increases. We introduce a configurable hybrid digital/analog micro-architecture capable of implementing a broad set of signal processing applications based on these concepts, together with a back-end optimizer which takes advantage of the special nature of these applications. For a set of five signal applications, we explore the different design tradeoffs and obtain an accelerator with an area cost of 1.63 mm 2 . On average, this accelerator requires only 2.3% of the energy of an Atom-like core to implement similar tasks. We then evaluate the accelerator resilience to transient faults, and its ability to trade accuracy for energy savings.

An Efficient Design of 3bit and 4bit Flash ADC

The performance of Flash Analog-to-Digital converter is greatly influenced by the choice of Comparator and Thermometer-toBinary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment using spectre simulator under 90nm technology. The pre simulation results for the design shows a low power dissipation of 87uw for the comparator and 1.05mW and 1.984mW power dissipation for 3-bit and 4-bit Flash ADC respectively. The circuit operates with an input frequency of 25MHz and 1.5V supply with a conversion time of 2.162ns and 6.182ns for 3-bit and 4-bit ADC respectively.

Entropy and Average Cost of AUH Codes

In this paper we address the class of anti-uniform Huffman (AUH) codes, also named unary codes, for sources with finite and infinite alphabet, respectively. Geometric, quasi-geometric, Fibonacci and exponential distributions lead to anti-uniform sources for some ranges of their parameters. Huffman coding of these sources results in AUH codes. We prove that, in general, sources with memory are obtained as result of this encoding. For these sources we attach the graph and determine the transition matrix between states, the state probabilities and the entropy. We also compute the average cost for these AUH codes.

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter

SUMMARY This paper demonstrates a pulse width controlled PLL without using an LPF. A pulse width controlled oscillator accepts the PFD output where its pulse width controls the oscillation frequency. In the pulse width controlled oscillator, the input pulse width is converted into soft thermometer code through a time to soft thermometer code converter and the code controls the ring oscillator frequency. By using this scheme, our PLL realizes LPF-less as well as quantization noise free operation. The prototype chip achieves 60 μm × 20 μm layout area using 65 nm CMOS technology along with 1.73 ps rms jitter while consuming 2.81 mW under a 1.2 V supply with 3.125 GHz output frequency.

Review of Josephson Waveform Synthesis and Possibility of New Operation Method by Multibit Delta–Sigma Modulation and Thermometer Code for Its Further Advancement

Review of Josephson Waveform Synthesis and Possibility of New Operation Method by Multibit Delta–Sigma Modulation and Thermometer Code for Its Further Advancement

Novel Threshold-Based Standard-Cell Flash ADC

This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.

Review of Josephson Waveform Synthesis and Possibility of New Operation Method by Multibit Delta–Sigma Modulation and Thermometer Code for Its Further Advancement

A method of AC waveform synthesis with quantum–mechanical accuracy has been developed on the basis of the Josephson effect in national metrology institutes, not only for its scientific interest but its potential benefit to industries. In this paper, we review the development of Josephson arbitrary waveform synthesizers based on the two types of Josephson junction array and their distinctive driving methods. We also discuss a new operation technique with multibit delta–sigma modulation and a thermometer code, which possibly enables the generation of glitch-free waveforms with high voltage levels. A Josephson junction array for this method has equally weighted branches that are operated by thermometer-coded bias current sources with multibit delta–sigma conversion.

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs

A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18- mum CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. The proposed on-chip transient-to-digital converter can be further combined with firmware cooperation to provide an effective solution to solve the system-level ESD protection issue in microelectronic systems equipped with CMOS ICs.

Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method

A dynamic element-matching (DEM) method, i.e., randomized thermometer coding (RTC), for low-cost current-steering digital-to-analog converter (DAC) design is proposed. The proposed RTC method exhibits randomized starting-element selection, consecutive-element selection, and low-element switching activity. It can be used to significantly suppress the harmonic distortion caused by a large mismatch of small-area transistors, and, thus, very low cost DACs can be realized. With the proposed RTC, a 14-bit current-steering DAC is implemented in a 1P6M 0.18- mum 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) exceeds 80 dB. The measurement results showed that RTC improves the SFDR by more than 16 dB. The DAC has an active area of less than 0.28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed DAC achieves a smaller active area than state-of-the-art 12- to 14-bit DACs.

Burst Error Recovery Method for LZSS Coding

Since the compressed data, which are frequently used in computer systems and communication systems, are very sensitive to errors, several error recovery methods for data compression have been proposed. Error recovery method for LZ77 coding, one of the most popular universal data compression methods, has been proposed. This cannot be applied to LZSS coding, a variation of LZ77 coding, because its compressed data consist of variable-length codewords. This paper proposes a burst error recovery method for LZSS coding. The error sensitive part of the compressed data are encoded by unary coding and moved to the beginning of the compressed data. After these data, a synchronization sequence is inserted. By searching the synchronization sequence, errors in the error sensitive part are detected. The errors are recovered by using a copy of the part. Computer simulation says that the compression ratio of the proposed method is almost equal to that of LZ77 coding and that it has very high error recovery capability.

Deciding expressive description logics in the framework of resolution

We present a decision procedure for the description logic SHIQ based on the basic superposition calculus, and show that it runs in exponential time for unary coding of numbers. To derive our algorithm, we extend basic superposition with a decomposition inference rule, which transforms conclusions of certain inferences into equivalent, but simpler clauses. This rule can be used for general first-order theorem proving with any resolution-based calculus compatible with the standard notion of redundancy.

Digital Encoder for RF Transmit Waveform Synthesizer

We are designing an encoder for conversion of a Nyquist-rate N-bit digital word into a high frequency stream of single-bit data, to enable a novel architecture for a digital waveform synthesizer. The multi-bit to single-bit data conversion is performed by a new encoding scheme called the ldquostaggered thermometer code.rdquo Similar to the delta-sigma code, the staggered thermometer code also pushes most of the quantization noise to higher frequencies which can be easily filtered out with a low-pass filter. This encoder, built with elementary RSFQ cells, relies only on the merger of periodic pulse streams of different frequencies, and therefore, is much simpler to implement than a delta-sigma modulator which requires an accumulator and a multi-bit feedback loop. To avoid the permanent energy loss associated with low-pass filtering of high frequency components of the single-bit data stream, we also implement a novel digital circuit that acts as an amplifier by converting the pulse density modulated data stream into a pulse width modulated data stream. This digital amplifier changes the frequency spectrum by concentrating the energy in the fundamental while reducing higher harmonics. We have designed and fabricated a 4-bit and a 7-bit encoder circuit with integrated digital amplifier, and have demonstrated its operation up to a clock speed of 12.8 GHz.

Quantitative temporal logics over the reals: PSpace and below

In many cases, the addition of metric operators to qualitative temporal logics (TLs) increases the complexity of satisfiability by at least one exponential: while common qualitative TLs are complete for NP or PSpace, their metric extensions are often ExpSpace-complete or even undecidable. In this paper, we exhibit several metric extensions of qualitative TLs of the real line that are at most PSpace-complete, and analyze the transition from NP to PSpace for such logics. Our first result is that the logic obtained by extending since-until logic of the real line with the operators ‘sometime within n time units in the past/future’ is still PSpace-complete. In contrast to existing results, we also capture the case where n is coded in binary and the finite variability assumption is not made. To establish containment in PSpace, we use a novel reduction technique that can also be used to prove tight upper complexity bounds for many other metric TLs in which the numerical parameters to metric operators are coded in binary. We then consider metric TLs of the reals that do not offer any qualitative temporal operators. In such languages, the complexity turns out to depend on whether binary or unary coding of parameters is assumed: satisfiability is still PSpace-complete under binary coding, but only NP-complete under unary coding.

Error Correcting Encoders for Parallel-Type ADCs

Full-parallel and folding and interpolation (F&I) ADCs have a bank of latched comparators, the output of which is a "thermometer code" in full-parallel ADCs and a "circular code" in F&I ADCs. These special codes have to be transformed into a binary code. Nonideal effects can originate more than one "0" to "1" transition in the thermometer or circular code, causing large errors in the output binary code. A comparison of existing error correction techniques is presented in this paper, which shows that 1st order error correction provides considerable performance improvement, without a significant increase of circuit complexity. Higher order correction in full-parallel ADCs using Wallace tree encoding is very effective, but has a high cost in terms of circuit area and power consumption. In this paper it is shown that Wallace tree encoding can be extended to F&I ADCs, and that this leads to a very compact circuit for higher order error correction in low and medium resolution ADCs. This is demonstrated by designing and simulating a 6-bit, 200 Msample/s F&I ADC which has low power consumption and a small area.

Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area <12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time.

Dynamic range and error tolerance of stochastic neural rate codes

An investigation is made of the statistical properties of unary stochastic rate codes, as employed in the implementation of pulsed neural networks. The dynamic range exhibits a reduced dependence on the representation time due to increased estimation errors from the variance in the stochastic encodings of the integers. At the same time, these codes exhibit improved tolerance to noise-induced bit errors. Comparisons are made with conventional integer arithmetic and with deterministic unary codes for neural networks, up to bit error rates as large as 0.3.