Abstract
This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.
Highlights
The aggressive technology scaling seen in recent years has helped improve the performance of many digital systems
This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC)
The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node
Summary
The aggressive technology scaling seen in recent years has helped improve the performance of many digital systems. Reduction in feature size often entails reduction in supply voltage which can cause problems in the design of analog circuits These are some of the reasons why designers are interested in moving certain modules from the analog domain into the digital domain. In order to convert analog modules into digital modules, ADC and digital to analog converters (DAC) are typically required to interface between the domains The design of these components typically requires a certain level of expertise and they require analog/mixed signal components. We propose a flash ADC that can be fully implemented using only standard-cells This approach helps to improve the high-speed conversion rate while maintaining comparable power consumption. This allows the designer to stay within the mature digital design flow and effectively reduce risks and time-to-market.
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