Design of Flash ADC using low offset comparator for analog signal processing application

Abstract

The analog to digital converters (ADCs) are used in high bandwidth applications such as communications, radar processing and data acquisition system. In this work, a 3-bit Flash ADC is designed on Cadence simulation software with 180nm CMOS technology. The important parameters of ADC are resolution, conversion time and power dissipation. Flash ADC converts analog input signal to digital output signal in one clock cycle. In this work, Flash ADC has been designed using two-stage operational amplifier as comparator, voltage divider circuit and priority encoder. The proposed prototype has been simulated with 2.8V supply voltage at 27°C. The simulation results for the design shows an overall power dissipation of 3.6947mW for flash ADC, 431.637μW for the comparator. The main advantage of the comparator used is its low input offset voltage of 7.84 mV. The gain of the two stage operational amplifier is 85dB with the Miller Compensation Capacitance of 800fF and load capacitance of 1pF. This ADC has high input signal voltage range which is 0 to 2.8V. Monte Carlo simulation is done for power dissipation with 300 samples. Process variation is done for the power dissipation at different corners.