Unclamped Inductive Switching Research Articles

Investigation of the avalanche ruggedness of SiC MPS diodes under repetitive unclamped-inductive-switching stress

State of the art freewheeling diodes are connected antiparallel with a switch like IGBT or MOSFET and for latter also with the internal body diode. The diodes have to be rugged enough to overcome temporary overvoltage and overcurrent conditions during transient operation. SiC merged pin Schottky (MPS) diodes are one of the superior contenders and thus it is essential to make investigations under high avalanche energy. In this work, an avalanche ruggedness of 20 A/1.2 kV SiC MPS diodes was investigated far beyond the specified maximum ratings of the device under unclamped inductive switching (UIS) measurement. The function of avalanche energy versus applied inductance was investigated under single event avalanche stress. The reliability under high repetitive avalanche energy was studied in detail. A forward voltage drift, change in the Schottky junction voltage and increase in the leakage current was observed after the high repetitive avalanche stress far beyond the safe operating area. Detailed failure analysis was made, focusing on the degradation of the metallization and possible stacking faults (SFs) in the SiC bulk. Furthermore, the temperature was determined as a function of the blocking voltage during avalanche stress.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests.

Degradation characteristics of SiC power devices for DC circuit breaker by repetitive unclamped inductive switching test

This paper investigates the degradation of SiC power devices for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. The ON resistance of SiC power devices such as MOSFET and JFET are lower compared with Si devices. Therefore, SiC power devices are suitable for use as DC circuit breakers. Several papers have discussed degradation of SiC power devices; however, few studies have determined a suitable power device for a DC breaker from a degradation standpoint. In this paper, four types of SiC devices were subjected to repetitive UIS tests. Our research demonstrated SiC-JFET to be suitable for a DC breaker.

Effect of Defects in Silicon Carbide Epitaxial Layers on Yield and Reliability

Inline metrology tools are widely used to detect defects in SiC epitaxial layers. The defect statistics are used in a variety of ways to determine quality, pass/fail and screen affected die. In this work, we document the automated detection and classification of various epitaxial defects based on type and origin. We further classify these categories into killer and non-killer defects and compare them to the electrical yield of Schottky Diodes. The origins of these defects are determined in broad categories, resulting in a clustering and yield-scaling model, which agrees very closely to experimental data. Further, we look at on-wafer screening techniques of potential weak die by both defect tagging and unclamped inductive switching (UIS) stress testing. Successful 1000-hr reliability tests show the robustness of our detection and screening methods.

Reliability and Ruggedness of Planar Silicon Carbide MOSFETs

The reliability and ruggedness of Monolith/Littelfuse planar SiC MOSFETs have been evaluated using constant voltage time-dependent dielectric breakdown for gate oxide wearout predictions, showing estimated > 100 year life at VGS=+25V and T=175C. Using extended time high-temperature gate bias, we have shown < 250 mV threshold voltage shifts for > 5000 hours under VGS=+25V and negligible threshold voltage shifts for > 2500 hours under VGS=-10V, both at T=175C. Under unclamped inductive switching, these 1200V, 80 mOhm SiC MOSFETs survive 1000 mJ of avalanche energy, meeting state-of-art ruggedness for 1200V SiC MOSFETs.

Avalanche Robustness of 4600 V SiC DMOSFETs

A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm2 SiC DMOSFETs under unclamped inductive switching (UIS) conditions is presented. Maximum single-pulse avalanche energies (EAS) as high as 1.07 J (13.75 J/cm2) and avalanche withstand times (tAV) as high as 71 μs are recorded. The variation of EAS and tAV with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including RDS,on, VTH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Different failure locations confined within the active area of the DMOSFETs are identified after avalanche failure for either low or high EAS failed devices and a tentative model to explain the failure physics is presented.

Avalanche Ruggedness Characterization of 10 kV 4H-SiC MOSFETs

In this paper, single pulse unclamped inductive switching (UIS) test of Wolfspeed Gen-3 10 kV, 15 A 4H-SiC MOSFETs is performed for four operating conditions at room temperature. The avalanche energy is observed to be around 7.0 J. The measured values are in good agreement with expected behavior, which may be extrapolated beyond the experimentally measured range. Failure analysis was conducted after each device failure to observe the failure locations. Avalanche parameters of SiC MOSFETs with various voltage ratings are compared. The avalanche energy of the Gen-3 10 kV, 15 A 4H-SiC MOSFETs is obtained to be superior to earlier generations of 10 kV SiC MOSFETs.

Comparative Study on the Repetitive Unclamped-Inductive-Switching Capability(R-UIS) of 1200V 160mOhm SiC Planar Gate MOSFETs

This paper presents the comparative study on the repetitive unclamped inductive load switching capabilites in comercialized 1200V, 160mΩ rated SiC MOSFETs. Recently released Littelfuse-Monolith 1200V 160 mOhm design (LSIC1MO120E0160) manufactured through 150mm high volume CMOS compatible process demonstrated excellent R-UIS capabilities: no parametric shift on key electrical performances such as on-resistance, threshold voltage, breakdown voltage and drain leakage current after 100000 cycles of R-UIS stress. Both Competitor A and B design with planar gate showed R-UIS capabilities. All critical parameters were within the datasheet specification after R-UIS test. Competitor A design was equivalent to LSIC1MO120E0160. Competitor B design showed the drain leakage increase after 2000 cycle of R-UIS stress. Competitor C design with trench gate did not exhibit any R-UIS capabilities.

Safe Operation of Maximum Temperature for Planar Gate SiC Mosfet under Avalanche Stress Shock

Avalanche capability is one of the most significant ruggedness concerns. In this paper, avalanche capability of 1200V 80mΩ CREE SiC MOSFET characterizing planar gate structure is assessed under unclamped inductive switching test with various loads (3.6mH, 1.1mH, 0.3mH). Through similar maximum withstanding avalanche energy for the three loads and failure behavior, the heat induced failure can be determined, even though very different maximum avalanche peak currents I av,pk and avalanche time t av. The increasing avalanche energy generates heat to rise device temperature until the maximum temperature approaches the metal system on the surface of SiC material. The maximum safe operation temperature for planar SiC MOSFET is determined by the metal melting point. The avalanche ruggedness of the SiC MOSFET provides related information to application design. The results can also help understand ultimate failure cause of avalanche shock and improve the ruggedness of device.

High-Temperature Impact-Ionization Model for 4H-SiC

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field.

Investigation on single pulse avalanche failure of SiC MOSFET and Si IGBT

In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

Effect of short circuit aging on safe operating area of SiC MOSFET

In this paper, we study the effect of aging of SIC MOSFETs on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energies, which allows to validate the relevance of evolution of different aging indicators measured during the aging process. The decrease in the dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to clearly link the evolution of these Safe Operating Areas to the degradation of electrical performances (drain and gate leakage currents and on-state resistance). Obtained results show that a strong increase in the drain and/or gate leakage currents after aging has a great effect on the decrease of Safe Operating Area especially on RBSOA and that on-state resistance increase due to aging process represents less impacts in the evolution of RBSOA than in the case of SCSOA. It is also clear from the obtained results that without any apparent evolution of these leakage currents, the decrease of SCSOA after aging is related to the increase in the on-state resistance.

Investigation of avalanche ruggedness of 650 V Schottky-barrier rectifiers

Avalanche breakdown of novel 650 V SiC Schottky-barrier rectifiers is investigated. The rectifier diode has low leakage current for the temperatures up to 300 °C. Thermal coefficient of avalanche breakdown increases with the temperature to around 0.009%/K at 200 °C. Near-uniform avalanche breakdown is verified using emission imaging, and maximum specific avalanche energy of 20.7 J/cm2 is achieved. The critical temperature for stability in unclamped inductive switching (UIS) is above 520 °C as estimated through thermal simulation. Long-term walkout of breakdown voltage at 176 °C is less than 0.02%.

Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

A Deep Insight Into the Degradation of 1.2-kV 4H-SiC mosfets Under Repetitive Unclamped Inductive Switching Stresses

In this paper, the long-term reliability of commercial 1.2-kV 4H-SiC mofset s under repetitive unclamped inductive switching stresses is evaluated experimentally. The degradation of device characteristics, including the threshold voltage $V_{{\rm{th}}}$ , drain leakage current $I_{{\rm{dss}}}$ , and on-state resistance $R_{{\rm{on}}}$ , is observed after 80k avalanche cycles. The regular charge pumping (CP) measurements reveal that the failure mechanism characterized by the hot holes injection and trapping into the gate oxide above the channel and JFET region may occur during the aging experiments, which is further ascertained by the succeeding electrothermal simulations and should be responsible for the degradation of $V_{{\rm{th}}}$ and $I_{{\rm{dss}}}$ . After decapping the failed devices, the bond wires lift off due to thermal fatigue is discovered and regarded as the main reason for the degradation of $R_{{\rm{on}}}$ . The poststress high-temperature treatment is also carried out as an approach to indirectly corroborate the aforementioned failure mechanisms. Moreover, the impact of different test conditions on the degradation rate of electrical characteristics is discussed to thereby find ways to relieve these degeneration phenomena.

A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device

An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus, the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N+ source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.

Extraction method of interfacial injected charges for SiC power MOSFETs

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

Investigation of Maximum Junction Temperature for 4H‐SiC MOSFET During Unclamped Inductive Switching Test

SUMMARYNormally, thermal breakdown is one of the serious failure phenomena in the power device application, which drives the researchers to focus on exploration of the failure mechanism and the new evaluation method for power device. In this paper, unclamped inductive switching test is presented to evaluate energy handing ability and maximum junction temperature of 1200 V/19 A SiC MOSFET during avalanche mode. It is verified that commercial 1200 V/19 A SiC MOSFET can easily withstand almost 10 μs avalanche time and around 924 K maximum junction temperature with 1 mH inductance and 400 V dc bus at the case temperature of 300 K in avalanche mode. In addition, three reasonable evaluation methods of the maximum junction temperature for SiC MOSFET are summarized at different case temperatures.

Single-Pulse Avalanche Mode Robustness of Commercial 1200 V/80 mΩ SiC MOSFETs

Commercialization of 1200-V silicon carbide (SiC) MOSFET has enabled power electronic design with improved efficiency as well as increased power density. High-voltage spikes induced in applications such as solenoid control, solid-state transformer, boost converter, and flyback converter can drive the MOSFET into avalanche mode operation due to high di / dt coupled with parasitic inductance. Avalanche mode operation is characterized by high-power dissipation within the device due to the high voltage and current crossover. This study focuses on the evaluation of two commercially available SiC MOSFETs from different manufacturers, each rated for 1200 V with an ON-state resistance of 80 mΩ, during unclamped inductive switching (UIS) mode operation. To determine device reliability, a decoupled UIS testbed was developed to evaluate the avalanche energy robustness at 22 $ \,^{\circ}$ C and 125 $ \,^{\circ}$ C during two specific conditions: high current and low energy, and low current and high energy. The SiC MOSFETs were evaluated using a load inductance of 1.42, 5.1, 10.5, and 15.8 mH to understand the effect of current and avalanche energy on device failure. To correlate the experimental results with the failure mechanism, estimated junction temperature and static device characteristics are presented; additionally, MOSFETs were decapsulated to examine the failure sites on the semiconductor die.

Trade-off analysis of the p-base doping on ruggedness of SiC MOSFETs

Reliability represents a very important factor for the design of Silicon Carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs). Ruggedness of the device during abnormal operating conditions like the short circuit (SC) and avalanche conduction (during unclamped inductive switching - UIS) is an important aspect of reliability. Often, variation in design parameters to improve ruggedness during SC and UIS shows negative impact on the nominal operating performance. This paper presents a comprehensive analysis of the impact of modification of p-base doping on the performance of a 1.2kV SiC MOSFET during SC and UIS by means of TCAD simulations. The improvement in MOSFET ruggedness by optimizing the p-base doping and its influence on the nominal operating performance is evaluated.