Um Process Research Articles

Design and Manufacture of Energy-Recycling Pads for Low-Power Chips

Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.

Analysis of the electrical characteristics of SCR-based ESD Protection Device (PTSCR) in 0.13/0.18/0.35um process technology

In this paper, an experimental analysis of the electrical characteristics of the PTSCR was conducted. The PTSCR contains a high trigger current and a holding voltage that enables latch-up immune during normal operation. The PTSCR in each process technology is verified by the TLP system as well as a hot chuck controller. The experimental results show that the trigger current and holding voltage are higher than that of other SCR devices. At higher temperatures, the holding voltage of the PTSCR decreased due to the operation mechanism of the SCR, while the trigger current increased due to the MOSFET trigger mechanism.

하드웨어와 소프트웨어의 역할 분담을 통해 칩 면적을 크게 줄인 Image Signal Processor의 설계

이미지 센서에서 획득된 영상에는 화질 개선을 위해 다양한 이미지 처리 과정이 필요하다. 이러한 이미지를 처리해 주는 역할을 하는 것을 ISP(Image Signal Processor)라고 한다. 기존의 비전 카메라는 상용 ISP 칩을 사용하는 대신에 자체적으로 ISP 기능을 소프트웨어로 구현하여 PC등에서 수행하는 방식을 택해왔다. 그러나 이러한 방식은 ISP 기능을 수행하는데 많은 연산을 필요로 함에 따라 고성능 PC를 필요로 하는 문제가 있다. 본 논문에서는 하드웨어와 소프트웨어의 효율적인 분담을 통해 칩 면적을 크게 줄인 ISP를 제안한다. 연산을 빠르게 처리하기 위하여 연산이 많은 블록은 하드웨어로 설계하였고, 하드웨어의 면적을 고려하여 하드웨어와 소프트웨어를 동시에 이용하도록 설계하였다. 구현된 ISP는 VGA(640*480)급의 영상을 처리할 수 있으며 0.35um 공정에서 91450 게이트의 크기를 가진다. The Image sensor needs various image processing to improve image quality. ISP(Image Signal Processor) performs various image processing. Conventional vision cameras have own software ISP functions and perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, we proposed ISP that significantly reduced chip area by efficient sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and we used hardware simultaneously with software considering the size of the hardware. The implemented ISP can process VGA(640*4800) images and has 91450 gate sizes in 0.35um process.

The DWA Design with Improved Structure by Clock Timing Control

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

A LOW DROPOUT LINEAR VOLTAGE REGULATOR CHIP, THE TH7150

A low dropout (LDO) linear voltage regulator, dubbed TH7150, is designed and reported. TH7150 is a power management device for analog chips, operating at low quiescent current (100uA), low voltage supply (1.6-3.6V), with low dropout voltage (200mV), and capable of driving 150mA output current. Its output voltage is programmable by logic control and also manually adjustable. It features protection measures for overheating and overloading and monitoring for the output voltage to prevent a dropout greater than 10% of current value. The chip is designed to be fabricated using 0.35 um process. It can be used as a standalone chip or integrated in a power supply chip for portable devices such as Smart phone, cell phone, Ipod, digital camera etc.

A novel low power time-mode comparator for successive approximation register ADC

A novel low power time-mode comparator with enhanced resolution and speed is proposed in this paper. The comparator incorporates a symmetrical input time-to-digital converter (TDC) and a highly dynamic voltage-to-time converter (VTC). Energy reduction is achieved mainly through the use of capacitor discharge automatic switch-off and inverter clocking. The combined effect of the low timing requirement and capacitor voltage presetting enables significant precision and speed improvements. Simulations in a 0.18um process show that the comparator can be clocked at 38MHz, draws less than 0.4pJ energy from supply and can resolve voltages as low as 10µV.

Optimized step-stacked-routing ESD diode and its effects on LNA minimum noise figure

Low capacitance loading is a continuous demand and challenge for ESD device design. In this research, an inter-digital ESD diode realized in TSMC 0.18um process is optimized and verified. The diode is capable of passing 7κV HBM with 190fF capacitance loading for dual diode protection scheme. Using the novel Step-Stacked-Routing technique, the capacitance is reduced by 18%. The effect on LNA minimum noise figure of this diode is analyzed and simulated with the extracted small signal model.

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelines. As several studies show, internal processor structures scale differently with decreasing device sizes. While in some cases the access latency is determined by the speed of the logic circuitry, for others it is dominated by the interconnect delay. Furthermore, while some stages can be super-pipelined with relatively small performance loss, others must be kept atomic. This paper proposes a possible solution to this problem, avoiding the traditional trade-off between parallelism and clock speed. First, allowing instructions to enter and leave the Issue Window in an asynchronously manner enables faster speeds in the front-end at the expense of small synchronization latencies. Second, using an Execution Cache for storing instructions that are already scheduled allows for bypassing the issue circuitry and thus clocking the execution core at higher frequencies. Combined, these two mechanisms result in a 50% to 60% performance increase for our test microarchitecture, without requiring a completely new scheduling mechanism. Furthermore, the proposed microarchitecture requires significantly less energy, with 30% reduction in a 0.13um or 20% in a 0.06um process technology over the original baseline.

Low power scalable encryption for wireless systems

Secure transmission of multimedia information (e.g., voice, video, data, etc.) is critical in many wireless network applications. Wireless transmission imposes constraints not found in typical wired systems such as low power consumption, tolerance to high bit error rates, and scalability. A variety of low power techniques have been developed to reduce the power of several encryption algorithms. One key idea involves exploiting the variation in computation requirements to dynamically vary the power supply voltage. Application of low power techniques to a wireless camera application yield more than an order of magnitude reduction in power consumption over conventional design methods. Test circuits for five algorithms have been fabricated in a 0.6 um process and the resulting power consumption of each is presented. In addition, a low power hybrid system that combines a power-efficient keystream generator with a secure pseudo-random seed generator is proposed that provides 1 Mbps data encryption at a total estimated power consumption of 150 uW.

Lithography system evolution: a perspective on a methodology for the rapid determination of 0.25um process capability.

Introduction of new semiconductor technology to the market place depends on how quickly advanced research and development organizations can provide viable products. A methodology is described and examples given that reduce the development time associated with leading edge lithography systems. An interactive development loop focusing on improvement of dimensional control and depth of focus is discussed. Techniques to improve the areas of design, data collection and analysis are presented.

The Effect of Operating Frequency in the Radiation Induced Buildup of Trapped Holes and Interface States in MOS Devices

Both n-channel and p-channel MOS transistors, fabricated with a radiation hardened 3-4 um process, were irradiated at various operating frequencies and biases. The n-channel devices showed a larger rebound effect when alternately biased 'off' and 'on' during irradiation than for the cases of being biased either 'off' or 'on' during the irradiation. The p-channel devices showed a smaller threshold voltage shift when alternately biased 'off' and 'on' during irradiation compared to devices which were biased either 'off' or 'on' during the irradiation. The contributions of trapped holes and interface states on the observed threshold voltage shifts were determined through subthreshold current measurements. This research showed the source of this alternating bias effect on the radiation response of MOS devices to be reduced hole trapping and increased interface state buildup in n-channel MOS devices. In p-channel devices, reduced hole trapping is the primary source of this effect.