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Abstract
Low capacitance loading is a continuous demand and challenge for ESD device design. In this research, an inter-digital ESD diode realized in TSMC 0.18um process is optimized and verified. The diode is capable of passing 7κV HBM with 190fF capacitance loading for dual diode protection scheme. Using the novel Step-Stacked-Routing technique, the capacitance is reduced by 18%. The effect on LNA minimum noise figure of this diode is analyzed and simulated with the extracted small signal model.
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