Ultrathin Interfacial Layer Research Articles

Analysis of ${\rm P}_{b}$ Centers in Ultrathin Hafnium Silicate Gate Stacks

A in the capacitance-voltage (C-V) characteristics of MOS capacitors with an ultrathin interfacial layer of 7-8 ? in a hafnium silicate gate dielectric is analyzed via high-low frequency C-V and quantum-mechanical calculations. Hole and electron traps (amphoteric) with energy levels determined at Ev+0.44 eV and Ev+0.89 eV are surmised to be Pb1 and Pb0 centers, respectively. Of these two defects, those in the lower half of the bandgap cause an asymmetric kink in the C-V characteristics that can further be attributed to an additional level at Ev+0.32 eV, corresponding to centers. With reducing temperatures, the peaks move toward the band edge with increasing magnitude, consistent with multiphonon emission models of capture behavior.

Wear-out and breakdown of rf sputtered Ta2O5 films on silicon

The evolution of the gate voltage during the constant current stress of Ta2O5 films grown on silicon exhibits an additional decreasing region, compared to the case of SiO2 films. That phenomenon has been previously attributed to the thickness lowering of the ultrathin SiO2 interfacial layer naturally grown during the Ta2O5 deposition. Based on the previously proposed method of the evolution of the capacity in accumulation with the stress time, a simplified phenomenological model of capacitors in series was developed and employed as a tool for monitoring the degradation of the insulating film. In some cases breakdown events manifested by abrupt changes of the capacity in accumulation were observed, e.g., the case with the voltage on the silicon dioxide films. In other cases, saturation of the capacity in accumulation was detected, indicating continuous degradation of the SiO2 layer till its final destruction. The above effect was not observed in SiO2 films and can be peculiar for Ta2O5/SiO2 or similar stacked layers.

Atomic transport and chemical stability of nitrogen in ultrathin HfSiON gate dielectrics

HfSiO and HfSiON films with thicknesses compatible with the requirements for gate dielectrics alternatives to SiO2 in ultra-large scale integration silicon-based CMOSFET devices were deposited on an ultrathin HfSiO15N interfacial layer on Si(001). These structures were submitted to thermal processing routines typical of post-deposition annealing and dopant activation steps in fabrication technology, namely at 450 or 1000 °C, respectively, and in atmospheres of N2 and/or O2. N transport and loss were determined by nuclear reaction analysis, including sub-nanometric depth resolution profiling with narrow nuclear reaction resonances. The chemical states of N were accessed by angle-resolved X-ray photoelectron spectroscopy. After annealing at 450 °C, N is seen to be mobile, whereas the chemical environment of N is not changed at this temperature. Annealing at 1000 °C renders N mobile and its most abundant chemical state in near-surface regions is unstable. Annealing in O2 atmosphere promotes incorporation of O from the gas phase into the films, partly in exchange for N and O atoms and partly by net incorporation of oxygen in the films. The profiles of the newly incorporated O atoms are also determined with sub-nanometric depth resolution by narrow nuclear reaction resonance profiling.

Efficient Polymeric Light-emitting Devices with Aluminum Cathode

AbstractBy blending poly(ethylene glycol) (PEG) into an electroluminescence (EL) polymer, significantly enhanced EL efficiency in a polymer light–emitting diode (PLED) with aluminum electrode was achieved. An orange-color-emitting PLED with 10 wt% PEG blending achieved device efficiencies exceeding 2.6 cd/A for a wide range of bias voltage, which is more than two orders of magnitude higher than that for a similar PLED without the PEG blending. A similar enhancement was observed by introducing PEG as an ultra-thin interfacial layer between the emissive polymer and the cathode. The enhancement was also observed for several different species of emissive polymers, and for blending with either PEG or poly(ethylene oxide) (PEO) with different molecular weights. The enhanced efficiency was a result of the reduction of electron injection barrier height at the cathode-polymer interface. It is believed that interfacial interaction that is specific to Al plays an important role in the enhancement mechanism.

Polarization loop deformations of an oxygen deficient Pb(Zr0.25,Ti0.75)O3 ferroelectric thin film

An epitaxial oxygen deficient Pb(Zr0.25,Ti0.75)O3 (PZT) thin film, which presented hysteresis loop with significant shift along the electric field axis and apparent polarization suppression, is investigated. Loop deformations are studied and entirely explained, both qualitatively and quantitatively by simulations including the effect of an ultrathin interfacial layer uniformly charged. The method developed in this paper is suitable to calculate not only the polarization due to the switching domains, but also all the characteristics of the space charge layer. The determination of the linear dielectric constant of the bulk ferroelectric layer does not require preparation of films with different thicknesses, unlike most of the methods proposed to date. Linear dielectric constant and thickness of the interfacial layer are in the range εil=80–130 and dil=8–12nm, respectively. On the other hand, a very large interfacial charge concentration (Nil of few 1026m−3) is obtained. For the studied PZT sample, hysteresis deformations are not attributable to pinning of domain walls, despite the large value of Nil, but rather to the interfacial space charge layer that screens the applied electric field and prevents the full switching of the ferroelectric domains.

The Effect of Interfacial Layers on High-Performance Gate Dielectrics Processed by RTP-ALD

In this paper we present the role of the ultrathin interfacial silicon-oxide layer on the performance of high-k dielectrics. We deposited by rapid thermal process atomic layer deposition (RTP-ALD) and studied the electrical conduction mechanism of the films. As the quality of the interfacial layer may seriously influence the performance of a high-dielectric-constant gate material, we designed a number of experiments to understand the role of the interfacial layer. Some of these experiments include the study of an identical thermal cycle with and without use of the precursor for the deposition of films. In the transmission electron microscopy (TEM) micrographs (especially in STEM-Z) the formation of amorphous silica and crystalline zirconia exhibit a distinct periodicity characteristic of spinodal decomposition. This feature, along with atomic-level sharpness of the interface, may hold the key to excellent electrical properties reported in this paper. The ultrathin interfacial silicon oxide layer has the ability to accommodate the strain between silicon and the mixed phase material without creating significant defects at the interface. © 2004 The Electrochemical Society. All rights reserved.

An equivalent heterojunction-like model for polysilicon emitter bipolar transistor

A new method was presented in this article to explain high current gain of polysilicon emitter transistor. By regarding interfacial oxide between polysilicon emitter and silicon emitter as a wide band gap material which can limit minority transport from silicon to polysilicon, thus improve emitter injection efficiency and increase current gain, the characteristics of RCA transistor (a ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) can be explained expediently. The theory also applied to HF transistor by treating difference band gap Δ E g between interfacial material and silicon as zero. Comparison between experimental and theoretical results was made and they are accordant. Through equivalent model Δ E g of a RCA transistor can be estimated as 101 meV.

Oxide formation and passivation for micro- and nano-electronic devices

A low-temperature remote plasma-assisted oxidation process for interface formation and passivation has been extended from Si and SiC to GaN. The process, which can be applied to nano-scale structures including quantum dots and wires, provides excellent control of ultra-thin interfacial layers which passivate the GaN substrate, preventing a parasitic or subcutaneous oxidation of the substrate during plasma deposition of SiO2. The remote plasma processing for GaN–SiO2 heterostructures includes: (i) an in situ nitrogen plasma surface clean; (ii) a remote plasma-assisted oxidation for formation of an interfacial GaOx (x=1.5) transition region between the GaN and deposited dielectric; and (iii) a remote plasma-enhanced chemical vapor deposition of an SiO2 dielectric.

Low temperature semiconductor surface passivation for nanoelectronic device applications

A low temperature remote plasma assisted oxidation (RPAO) process for interface formation and passivation has been extended from Si and SiC to GaN. The process, which can be applied to nanoscale structures including quantum dots and wires, provides excellent control of ultra-thin interfacial layers which passivate the GaN substrate, preventing a parasitic or subcutaneous oxidation of the substrate during plasma deposition of SiO 2. This remote plasma processing for GaN-dielectric heterostructures includes: (i) an in situ nitrogen plasma surface clean, (ii) RPAO for formation of an interfacial GaO x transition region between the GaN and deposited dielectric, and (iii) a remote plasma enhanced chemical vapor deposition of an SiO 2 dielectric.

Preparation and Characterization of High-k Praseodymium and Lanthanoid Oxide Thin Films Prepared by Pulsed Laser Deposition

Several lanthanoid oxide thin films such as those of PrOx, Sm2O3, Tb4O7, Er2O3 and Yb2O3 have been prepared on Si(100) wafers by the pulsed laser deposition method (PLD). PrOx film shows thin SiO2-equivalent oxide thickness (EOT) and low leakage current simultaneously. On the other hand, SmOx thin film does not show good properties. It is revealed by XPS spectra of the PrOx film that the deposition in O2 ambient of 0.2 Torr produces an interfacial SiO2 or silicate layer. The sample deposited in a high vacuum at RT has only an ultra-thin interfacial layer, but hysteresis in the C–V characteristic and leakage current are large. Other techniques have been carried out to reduce the energy of ablated particles in order to prevent the growth of an interfacial layer. In the deposition method using a shadow mask, very flat thin films were obtained. However, the deposition rate was very low, and growth of the interfacial layer could not be prevented. By enlarging the distance between substrate and target, the smallest EOT with the PrOx film in our study has been obtained by the reduction of the energy of ablated particles.

Synchrotron x-ray scattering study of SnO2 thin film grown on sapphire

From synchrotron x-ray scattering measurements, it was found that epitaxially grown SnO2 film on sapphire has a variant structure with threefold symmetry with respect to the substrate and that the ultrathin interfacial layer is formed due to the lattice mismatch between SnO2 and Al2O3. The physical properties of the top surface, such as surface morphology, height profile, and roughness, were determined by atomic force microscopy. The height profiles of the film grown at 600 °C and room temperature revealed the asymmetrical and the ordinary symmetric Gaussian distributions, respectively. The difference originates from the dominant diffusion process at high substrate temperature.

Formation mechanism of the multilayered-structure barrier of WNx/Si(100)

The chemical bonding states, microstructure, and the formation mechanism of an interfacial layer between WNx/Si(100) treated by rapid thermal annealing at various temperatures were investigated. It was found that the ultrathin interfacial layer had the multilayered structure of SiO2/SiOxNy/nano-WSi2. The interfacial silicon nitride layer formed by lower annealing temperatures was converted into an oxide layer by increasing the annealing temperature. The thickness of the interfacial oxide layer increased from ∼34 to ∼50 Å with the annealing temperature. It was found that the interfacial layer played a role as a barrier against silicidation between W and Si(100) up to 1000 °C.

Improvement of RCA transistor using RTA annealing after the formation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 /spl times/ 8 /spl mu/m/sup 2/. The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively.

Study on Zr-silicate interfacial layer of ZrO2 metal-insulator-semiconductor structure

We have investigated the physical and dielectric properties of the Zr-silicate interfacial layer of ZrO2 metal-insulator-semiconductor (MIS) structure fabricated by pulsed-laser ablation deposition. It was found that an ultrathin Zr-silicate interfacial layer is formed on a Si substrate as a result of the reaction between ZrO2 and Si. We showed that MIS capacitors consisting solely of the ultrathin Zr-silicate interfacial layer could be fabricated by selective etching of the ZrO2 layer. The Zr-silicate interfacial layer showed a small equivalent oxide thickness of 0.8 nm, a dielectric constant of 8–9, and low leakage less than 1 A/cm2 at Vg of −1 V.

Mechanism of the Suppression of Zr Silicide Formation in Poly-Si/ZrON/ZrSiON/Si Structure

AbstractIn this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfacial-layer/Si structure at 1000°C annealing are discussed in detail. It was demonstrated that gaseous SiO desorption, which played a dominant role in the silicide formation in the case of the ZrO2/SiO2/Si, was completely inhibited in the ZrON/interfacial-layer/Si structure. In addition, we have found that an ultrathin interfacial SiON layer between poly-Si and ZrON stabilized the interface. Consequently, we concluded that the effective nitrogen incorporation into top/bottom interfacial SiON layers with our process was responsible for the superior thermal stability of the stack.

Preparation of bipolar membranes. II

The bipolar multilayer membrane was prepared by a new technique. The interfacial layer and cation layer were formed by only one step. The anion and cation layers were made from the same material from which chloromethylated polysulfone was used as a basic material. The bipolar membranes were composed of a solvent-resistant anion layer with crosslinking matrix by the reaction of chloromethylated polysulfone in DMF with diamine; an ultrathin interfacial layer from chloromethylated polysulfone solution in DMF, containing cation-exchange resin and both quaternary and nonquaternary amine groups; and a cation layer from chloromethylated polysulfone dispersing cation resin powder. The prepared bipolar membrane exhibits a lower voltage drop over 100 mA/cm2 and stable performances at a long-term operation. © 2001 John Wiley & Sons, Inc. J Appl Polym Sci 82: 1733–1738, 2001

Preparation of bipolar membranes. II

AbstractThe bipolar multilayer membrane was prepared by a new technique. The interfacial layer and cation layer were formed by only one step. The anion and cation layers were made from the same material from which chloromethylated polysulfone was used as a basic material. The bipolar membranes were composed of a solvent‐resistant anion layer with crosslinking matrix by the reaction of chloromethylated polysulfone in DMF with diamine; an ultrathin interfacial layer from chloromethylated polysulfone solution in DMF, containing cation‐exchange resin and both quaternary and nonquaternary amine groups; and a cation layer from chloromethylated polysulfone dispersing cation resin powder. The prepared bipolar membrane exhibits a lower voltage drop over 100 mA/cm2 and stable performances at a long‐term operation. © 2001 John Wiley & Sons, Inc. J Appl Polym Sci 82: 1733–1738, 2001

Sign reversal of spin polarization inCo/Ru/Al2O3/Comagnetic tunnel junctions

Utilizing ultrathin Ru interfacial layers in ${\mathrm{C}\mathrm{o}/\mathrm{A}\mathrm{l}}_{2}{\mathrm{O}}_{3}/\mathrm{Co}$ tunnel junctions, we demonstrate that not only does the tunnel magnetoresistance decrease strongly as the Ru thickness increases as found for Cu or Cr interlayers, in contrast, even the sign of the apparent tunneling spin polarization may be changed. Further, the magnitude and sign of the apparent polarization is strongly dependent on applied voltage. The results are explained by a strong density-of-states modification at the (interdiffused) Co/Ru interface, consistent with theoretical calculations and experiments on Co/Ru metallic multilayers and Co-Ru alloys.

Interlayer Mediated Epitaxy of Cobalt Silicide on Silicon (100) from Low Temperature Chemical Vapor Deposition of Cobalt Formation Mechanisms and Associated Properties

This paper reports the development of a methodology for the growth of epitaxial that uses Co films deposited by low temperature (390°C) chemical vapor deposition (CVD) from cobalt tricarbonyl nitrosyl as source precursor. This CVD process exploits the reaction kinetics associated with the adsorption and decomposition of on Si surfaces to ensure the in situ, sequential growth of an ultrathin interfacial oxide layer followed by a Co thin film in a single deposition step. It is demonstrated that this interlayer, consisting of a Si-O or a Co-Si-O phase, inhibits silicidation for uncapped CVD Co regardless of annealing times and temperatures. Instead, Co agglomeration is observed, with the degree of agglomeration being proportional to the annealing temperature. The agglomeration is due to a reduction in the overall energy of the system through decrease of the Co/substrate interfacial area. Alternatively, for Ti/TiN capped CVD Co samples, the interfacial layer appears to play a role similar to that observed for similar layers in interlayer mediated epitaxy (IME). This assessment is supported by the observation of epitaxial for capped CVD Co samples after a single-step anneal at 725°C for 30 s. In contrast, Ti/TiN capped PVD Co samples annealed under identical processing conditions exhibited a polycrystalline phase with a strong (200) texture. As such, the methodology presented herein represents a modified IME technique for the growth of high quality, epitaxial films for applications in emerging microelectronics device technologies. © 2000 The Electrochemical Society. All rights reserved.

Separate and independent reductions in direct tunneling in oxide/nitride stacks with monolayer interface nitridation associated with the (i) interface nitridation and (ii) increased physical thickness

Direct tunneling limits aggressive scaling of thermally grown oxides to about 1.6 nm, a thickness at which the tunneling current density Jg at 1 V is ∼1 A/cm2. This article demonstrates that stacked gate dielectrics prepared by remote plasma processing and including (i) ultrathin nitrided SiO2 interfacial layers and (ii) either silicon nitride or oxynitride bulk dielectrics can extend the equivalent oxide thickness to 1.1–1.0 nm before Jg exceeds 1 A/cm2. Significant reductions in direct tunneling are derived from (i) interface nitridation at the monolayer level and (ii) the increased physical thickness of the nitride or oxynitride alloy layers. The “portability” of the interface contribution is demonstrated by combining the nitrided SiO2 interface layers with transition-metal oxides, e.g., Ta2O5, in stacked gate dielectric structures and obtaining essentially the same reductions in tunneling current on n- and p-type substrates with respect to non-nitrided plasma-grown interface layers.