Ultrathin Interfacial Layer Research Articles

Electrical properties of HfO2/La2O3 gate dielectrics on Ge with ultrathin nitride interfacial layer formed by in situ N2/H2/Ar radical pretreatment

In situ N2/H2/Ar radical pretreatment on p-type Ge (100) with HfO2/La2O3 high-κ gate oxide was investigated by remote rf plasma on radical-assisted atomic layer deposition. The interfacial LaGeOxNy formation and Ge outdiffusion were also investigated by x-ray photoelectron spectroscopy and transmission electron microscopy. The high-κ MOS device with an ultrathin LaGeOxNy interfacial layer shows good electrical characteristics, including larger κ value, smaller equivalent oxide thickness, lower leakage current density, smaller C-V hysteresis, and lower interface-state density. The involved mechanism lies in that the LaGeOxNy interfacial layer can effectively block Ge outdiffusion, thus improving the high-κ films/Ge interface quality.

Degradation and breakdown characteristics of Al/HfYOx/GaAs capacitors

Effects of surface passivation and the interfacial layer on the reliability characteristics of Al/HfYOx/GaAs metal-oxide-semiconductor capacitor structures are reported. Stress-induced leakage current mechanism, critical for understanding the degradation and breakdown in Al/HfYOx/GaAs capacitors, has been studied in detail. While the devices fabricated with (NH4)2S-passivated GaAs substrates show both the soft and hard breakdown failure modes, capacitors with ultrathin interfacial layer (Ge or Si) show only hard breakdown. It is shown that the degradation dynamics follows more closely the logistic power-law relationship rather than the conventional power-law model, frequently used to describe leakage current conduction in high-k gate dielectrics.

Pr3Si6N11/Si3N4 Stacked High-k Gate Dielectrics with High Quality Ultrathin Si3N4 Interfacial Layers

In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any crystal orientation silicon surface with the same formation speed, i.e., the radical oxidation (SiO2) and the radical nitridation (Si3N4) at low temperatures. Accumulation mode balanced CMOS fabricated on (551) surface silicon SOI substrate has been theoretically confirmed to exhibit super high speed performance over 100 GHz clock rate at 45 nm technology node where the gate insulator film to silicon interface is atomically flat and the series resistance of the source and the drain electrode is decreased by a factor of two orders of magnitude by introducing very low contact resistance new silicide materials to n+ region (ErSi2) and p+ region (Pr2Si), respectively.

Pr3Si6N11/Si3N4 Stacked High-k Gate Dielectrics with High Quality Ultrathin Si3N4 Interfacial Layers

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(Invited) Dye-Sensitized Solar Cell Photoelectrode Fabrication and Modification by Atomic Layer Deposition

Dye-sensitized solar cells (DSSCs) are a class of photoelectrochemical devices with exceptional potential for low-cost, scalable solar energy conversion. The ~10-um-thick sintered nanoparticle film that often comprises the photoelectrode is utilized to chemically bind ~1017 chromophores with monolayer coverage. Although this ingenious architecture allows DSSCs to achieve power conversion efficiencies of 12%, it is the chief obstacle to further advances in the field. Alternative photoelectrode designs attainable by atomic layer deposition (ALD) have opened new routes to efficiency improvement. Ultra-thin interfacial layers grown by ALD have also been utilized to tailor the properties of the large, heterogeneous junction universal to DSSCs.

Interfacial organic layers: Tailored surface chemistry for nucleation and growth

The interfaces between inorganic and organic materials are important to a wide variety of technologies. A significant challenge concerns the formation of these interfaces when the inorganic layer must be grown on a pre-existing organic layer. In this review the authors focus on fundamental aspects of inorganic-organic interface formation using transition metal coordination complexes and atomic layer deposition. First, the authors discuss aspects of the synthesis and characterization of ultrathin interfacial organic layers, formed mostly on SiO2 and possessing a variety of functional groups, including layers with a branched microstructure. The authors go on to discuss the reactions of transition metal coordination complexes with these layers. A number of factors control the uptake of the transition metal complex and the composition of the adsorbed species that are formed. These include the identity, density, and dimensionality or spatial distribution of the functional groups. At room temperature, adsorption on layers that lack functional groups results in the penetration of the organic layer by the transition metal complex and the reaction with residual OH at the organic/SiO2 interface. Adsorption on layers with a mostly two-dimensional arrangement of reactive functional groups results in the formation of molecular “bipods,” where the surface bound functional groups react with the complex via two ligand exchange reactions. In contrast, for layers that possess a high density of functional groups arranged three dimensionally, the transition metal complex can be virtually stripped of its ligands. Atomic layer deposition on interfacial organic layers also depends strongly on the density and accessibility of reactive functional groups. On surfaces that possess a high density of functional groups, deployed two dimensionally, growth via atomic layer deposition is initially weakly attenuated, mostly uniform and smooth, and eventually evolves to growth characteristic of unmodified SiO2. Growth on layers that lack sufficient densities of functional groups is initially strongly attenuated, in contrast, and the resulting films are rough, severely islanded and three dimensional. As a consequence, there is a correlation between the strength of the initial attenuation in the rate of growth and the thin film morphology. Correlations between the initial uptake of the transition metal complex by the organic layer and the initial rate of thin film growth are less direct, however, as the composition and structure of the chemisorbed species must also be considered.

Ultralow-Power TFT With Gate Oxide Fabricated by Nitric Acid Oxidation Method

We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain current-voltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 12-15 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

Magnetic Tunnel Junctions With $\hbox{Co:TiO}_{2}$ Magnetic Semiconductor Electrodes

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Spin-polarized tunneling is investigated in magnetic tunnel junctions containing an ultrathin interfacial layer of <formula formulatype="inline"> <tex Notation="TeX">$\hbox{Co:TiO}_{2}$</tex></formula> magnetic semiconductor. The <formula formulatype="inline"><tex Notation="TeX">$\hbox{Co:TiO}_{2}$</tex> </formula> layers (0 to 1 nm thick) are inserted at the <formula formulatype="inline"> <tex Notation="TeX">$\hbox{SrTiO}_{3}/\hbox{Co}$</tex></formula> interface in <formula formulatype="inline"><tex Notation="TeX">$\hbox{La}_{0.67}\hbox{Sr}_{0.33}\hbox{MnO}_{3}/\hbox{SrTiO}_{3}/\hbox{Co}$</tex> </formula> tunnel junctions. For all junctions we find a negative tunnel magnetoresistance, which decreases upon the insertion of <formula formulatype="inline"><tex Notation="TeX">$\hbox{Co:TiO}_{2}$</tex> </formula>, while the junction resistance increases strongly. This suggests that the ultrathin <formula formulatype="inline"><tex Notation="TeX">$\hbox{Co:TiO}_{2}$</tex> </formula> is a paramagnetic insulator that acts as an additional tunnel barrier, in contrast to thick (180 nm) layers grown under comparable conditions, which exhibit metallic impurity band conduction and room-temperature ferromagnetism. </para>

HfO 2-based gate stacks transport mechanisms and parameter extraction

Transport mechanisms through SiO 2/HfO 2 gate stacks have been investigated by means of Capacitance–Voltage ( C– V), Current–Voltage ( I– V) in a large range of temperature (80–400 K) and Transmission Electron Microscopy (TEM) measurements, on several nMOS transistors featuring different interfacial layer and HfO 2 thicknesses. The temperature dependency of experimental gate leakage currents have been found to be very weak when plotted versus total charge, except on thicker stacks, in inversion regime, between 300 and 400 K. Experiments have been compared with Direct Tunneling current (DT) simulations in inversion regime, using as few as possible arbitrary assumptions and fitting parameters. This comparison has shown that ultra-thin interfacial layer differs from pure SiO 2 only below 1 nm thickness, confirming previous theoretical works.

Improved electrical and interfacial properties of RF-sputtered HfAlO x on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO x gate dielectric. It is found that HfAlO x /Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10 12 eV −1 cm −2). The current density of 3.7 × 10 −5 A/cm 2 is achieved with an equivalent-oxide-thickness of 1.8 nm at V FB + 1 V for Si-passivated HfAlO x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole–Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.

Controlled Growth of High‐Quality ZnO‐Based Films and Fabrication of Visible‐Blind and Solar‐Blind Ultra‐Violet Detectors

AbstractZnO is a wide‐bandgap (3.37 eV at room temperature) oxide semiconductor that is attractive for its great potential in short‐wavelength optoelectronic devices, in which high quality films and heterostructures are essential for high performance. In this study, controlled growth of ZnO‐based thin films and heterostructures by molecular beam epitaxy (MBE) is demonstrated on different substrates with emphasis on interface engineering. It is revealed that ultrathin AlN or MgO interfacial layers play a key role in establishing structural and chemical compatibility between ZnO and substrates. Furthermore, a quasi‐homo buffer is introduced prior to growth of a wurtzite MgZnO epilayer to suppress the phase segregation of rock‐salt MgO, achieving wide‐range bandgap tuning from 3.3 to 4.55 eV. Finally, a visible‐blind UV detector exploiting a double heterojunction of n‐ZnO/insulator‐MgO/p‐Si and a solar‐blind UV detector using MgZnO as an active layer are fabricated by using the growth techniques discussed here.

Interfacial layer dependence on device property of high-κ TiLaO Ge/Si N-type metal-oxide-semiconductor capacitors at small equivalent-oxide thickness

We have investigated the device property dependence of high dielectric-constant (high-κ) TiLaO epitaxial-Ge/Si n-type metal-oxide-semiconductor (n-MOS) capacitors on different GeO2 and SiO2 interfacial layers. Large capacitance density of 3.3 μF/cm2, small equivalent-oxide thickness (EOT) of 0.81 nm and small C-V hysteresis of 19 mV are obtained simultaneously for MOS capacitor using ultrathin SiO2 interfacial layer, while the device with ultrathin interfacial GeO2 shows inferior performance of larger 1.1 nm EOT and poor C-V hysteresis of 93 mV. From cross-sectional transmission electron microscopy, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy analysis, the degraded device performance using GeO2 interfacial layer is due to the severe Ge outdiffusion, thinned interfacial GeO2 and thicker gate dielectric after 550 °C rapid-thermal anneal.

Structural and electrical properties of HfO 2/Dy 2O 3 gate stacks on Ge substrates

In the present work we report on the structural and electrical properties of metal–oxide–semiconductor (MOS) devices with HfO 2/Dy 2O 3 gate stack dielectrics, deposited by molecular beam deposition on p-type germanium (Ge) substrates. Structural characterization by means of high-resolution Transmission Electron Microscopy (TEM) and X-ray diffraction measurements demonstrate the nanocrystalline nature of the films. Moreover, the interpretation of the X-ray reflectivity measurements reveals the spontaneous growth of an ultrathin germanium oxide interfacial layer which was also confirmed by TEM. Subsequent electrical characterization measurements on Pt/HfO 2/Dy 2O 3/p-Ge MOS diodes show that a combination of a thin Dy 2O 3 buffer layer with a thicker HfO 2 on top can give very good results, such as equivalent oxide thickness values as low as 1.9 nm, low density of interfacial defects (2–5 × 10 12 eV − 1 cm − 2 ) and leakage currents with typical current density values around 15 nA/cm 2 at V g = V FB − 1 V.

Design of High-k Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing Method

We have developed a process for forming an ultra-thin high-k interfacial layer (HfSiOx-IL or AlSiOx-IL) for high-k gate stacks. The HfSiOx-IL and AlSiOx-IL was grown by Cycle-by-Cycle Deposition & Annealing method (this method is called CC-D&A, and the IL deposited by this method is called CC-IL). This method utilizes the solid-phase reaction between high-k films (HfO2 or Al2O3) and Si-substrate performed by repeating the sequence of 1 cycle ALD HfO2 (or Al2O3) deposition and RTA. The CC-IL enables the formation of very uniform films consisting of a few mono-layers. In this paper, we demonstrated the physical properties for CC-IL, and electrical properties for high-k gate stacks with CC-IL, and we achieved 0.5nm-EOT high-k gate stacks of CMOS with gate-first process.

Electroluminescence and impedance analyses of organic light emitting diodes using anhydride materials as cathode interfacial layers

Pyromellitic dianhydride (PMDA) and trimellitic anhydride (TMA) were tried as cathode interfacial layers between tris-(8-hydroxyquinoline) aluminum (Alq 3) and Al in organic light emitting diodes (OLEDs). Both ultra-thin anhydride cathode interfacial layers improved the electroluminescence characteristics of OLEDs compared to those without any interfacial layer, and the PMDA interfacial layer showed the most significant enhancement of the device performance. According to impedance measurements and equivalent circuit analysis, the PMDA interfacial layer decreased the impedance, probably due to the increase in the injection efficiency of electrons from the Al cathode.

Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application

Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge was obtained as a result of Fermi level depinning, and almost ideal Schottky barrier height determined by the work function difference between the metal and Ge was achieved. This technology was finally applied to metal source/drain Ge metal-oxide-semiconductor field-effect-transistors with low source/drain resistance.

Effects of AlAs interfacial layer on material and optical properties of GaAs∕Ge(100) epitaxy

Ga As ∕ Al As ∕ Ge ( 100 ) samples grown at 650°C with AlAs interfacial layer thickness of 0, 10, 20, and 30nm were characterized using transmission electron microscopy, secondary ion mass spectrometry (SIMS), and photoluminescence (PL) techniques. SIMS results indicate that the presence of an ultrathin AlAs interfacial layer at the GaAs∕Ge interface has dramatically blocked the cross diffusion of Ge, Ga, and As atoms, attributed to the higher Al–As bonding energy. The optical quality of the GaAs epitaxy with a thin AlAs interfacial layer is found to be improved with complete elimination of PL originated from Ge-based complexes, in corroboration with SIMS results.

Improved Electrical Properties of Gd2O3 ∕ GaAs Capacitor with Modified Wet-Chemical Clean and Sulfidization Procedures

In this study we demonstrated improved electrical characteristics of dielectric thin films on n-GaAs substrate by manipulating wet-chemical clean and passivation. With X-ray photoelectron spectroscopy analysis, the HCl-cleaned GaAs surface was characterized to possess oxide species mainly in the form of near the outmost surface and with elemental arsenic close to the interface. These undesirable components could be suppressed through rinsing in alkaline solution and then performing sulfidization at , resulting in alleviating the Fermi level pinning effect on capacitor performance. Higher oxide capacitance and alleviated frequency dispersion at the accumulation/depletion regimes were achieved, accompanied by negligible charge trapping . Accordingly, gate leakage was lowered to ca. at gate voltage , which was comparable to the recently reported performance of structure with an ultrathin interfacial layer. We attributed the electrical improvements to the enhanced stabilization of high-/sulfur-terminated GaAs interface due to abatement of native oxides and excess arsenic segregation.

TiO2/GeOxNy stacked gate dielectrics for Ge-MOSFETs

In this work, we present the results of physical and electrical characterization of Ti-based high-k gate dielectrics on Ge substrates. Titanium tetrakis iso- propoxide (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO2 films on p-Ge (1 0 0) at low temperature (<200 °C) by plasma enhanced chemical vapor deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of ∼65 Pa. The presence of an ultra-thin lossy GeO2 interfacial layer between the deposited high-k film and the substrate, results in frequency-dependent capacitance–voltage (C–V) characteristics in strong accumulation and a high interface state density (∼1013 cm−2 eV−1). To improve the electrical properties, nitrogen engineering has been employed to convert the lossy GeO2 interfacial layer to its oxynitride, thus forming TiO2/GeOxNy/Ge stacked-gate structure with improved interface/electrical properties. Different N sources, such as NO, NH3 and NO/NH3, have been used for nitrogen engineering. XPS and Raman spectroscopy analyses have been used for surface morphological study. Electrical properties, such as gate leakage current density, interface state density, charge trapping, flatband voltage shift, etc, have been studied in detail for TiO2/GeOxNy/Ge MIS capacitors using the current–voltage (I–V), capacitance–voltage (C–V), conductance–voltage (G–V) and stress (both constant voltage and current) measurements. Although a significant improvement in electrical characteristics has been observed after nitridation in general, the formation of the interfacial GeOxNy layer, obtained from NO-plasma nitridation, is found to provide the maximum improvement among all the nitridation techniques used in this study. It is shown that the insertion of an ultra-thin oxynitride (GeOxNy) interfacial layer is advantageous for producing gate-quality TiO2 high-k dielectric stacks on Ge substrates.

Analysis of ${\rm P}_{b}$ Centers in Ultrathin Hafnium Silicate Gate Stacks

A in the capacitance-voltage (C-V) characteristics of MOS capacitors with an ultrathin interfacial layer of 7-8 ? in a hafnium silicate gate dielectric is analyzed via high-low frequency C-V and quantum-mechanical calculations. Hole and electron traps (amphoteric) with energy levels determined at Ev+0.44 eV and Ev+0.89 eV are surmised to be Pb1 and Pb0 centers, respectively. Of these two defects, those in the lower half of the bandgap cause an asymmetric kink in the C-V characteristics that can further be attributed to an additional level at Ev+0.32 eV, corresponding to centers. With reducing temperatures, the peaks move toward the band edge with increasing magnitude, consistent with multiphonon emission models of capture behavior.