Ultrathin Dielectric Layers Research Articles

Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers

We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers.

Breakdown in ALD-processed oxide based thin film structures

ABSTRACTWe report on the continuous increase of the breakdown electric field, also known as disruptive strength, of an ultra thin layer based on Al2O3 prepared by atomic layer deposition (ALD) by reducing its thickness from 90 nm down to 3 nm. By calculating the disruptive strength for lower thicknesses, we demonstrate that our observations are in agreement with recent reports. Additionally, the disruptive strength increases to lower thicknesses as the pinhole density rises. The pinholes, referred to as morphological defects, are detected by Cu electroplating and result in a lower permittivity of the dielectric. As a conclusion, the dielectric breakdown is predominantly attributed to intrinsic, meaning stoichiometric defects. Thus, morphological defects, consisting of pinholes generated by agglomerative growth of the dielectric, surprisingly do not have a negative influence on the dielectric breakdown of ALD-processed ultra thin dielectric layers.

Towards high frequency performances of ultra-low voltage OTFTs: Combining self-alignment and hybrid, nanosized dielectrics

By combining an ultra-thin dielectric layer with a self-aligning process, an ultra-low voltage Organic Thin-Film Transistor (OTFT) with a 100kHz cutoff frequency was obtained. The devices are fabricated using a single-mask, photolithographic self-alignment technique compatible with the use of standard photoresists and not requiring any further chemical treatment. This technique allows a dramatic reduction of the parasitic capacitances thus leading to a remarkable increase of the cutoff frequency, even with organic semiconductors with a relatively low mobility. These characteristics make the reported approach suitable for the fabrication of basic building blocks for high frequency applications. In this paper, the main electrical parameters of ultra-low voltage, self-aligned devices are reported, and their complete frequency characterization is provided.

Characterization of defect evolution in ultrathin SiO2 layers under applied electrical stress

The structural evolution of ultrathin dielectric SiO2 layers within a Co-silicide/poly-Si/SiO2/Si multilayer system was studied by in situ transmission electron microscopy (TEM). The interface structure represents a model system for field effect transistors with a SiO2 dielectric layer. Electrical bias was applied across the interfaces of cross sectional TEM samples using a scanning tunneling microscopy (STM) tip. Atomic structure modifications of the dielectric layer due to the applied electrical field were observed by this in situ STM-TEM technique. Constant bias (+5.0 V) and ramped bias (+3.0 to +10.5 V) stresses applied to the CoSi2 gate electrode resulted in a loss in capacitance of the dielectric layer consistent with descriptions of soft dielectric breakdown (SBD) and hard dielectric breakdown (HBD). It was found that SBD events are characterized by fluctuations within uniform current step increase of 21 nA and increased roughness of the SiO2 film due to oxygen vacancy percolation. HBD, however, was found to be preceded by multiple SBD events between +6.5 V and +10 V, cobalt atom migration into the dielectric layer, partial crystallization of the amorphous gate dielectric (dielectric breakdown induced epitaxy), and significant diffusion of oxygen from the SiO2 layer into the silicon substrate through a reduction-oxidation reaction of the Si/SiO2 interface. Experimental results demonstrate the feasibility of in situ STM-TEM experiments for studying time-dependent dielectric breakdown behaviors to obtain a direct correlation of individual defect structures and their corresponding electrical signatures. Experimental limitations of this new technique are critically discussed.

Control of Schottky barrier heights by inserting thin dielectric layers

The insertion of ultra-thin dielectric layers to lower n-type Schottky barrier heights is shown to partly involve the creation of a net interfacial dipole as well as unpinning of the Fermi level by suppression of metal-induced gap states. The existence of a net dipole requires a lack of cancellation of dipoles at the two interfaces. This requires a different metal(Ge)-O bond density at the two interfaces, in general requiring differing oxygen chemical potentials. This would need the inserted dielectric to be a diffusion barrier, not just able to create dipoles, favoring the use of Al2O3-based or nitrided dielectrics.

Near-edge x-ray absorption fine structure spectroscopy studies of charge redistribution at graphene/dielectric interfaces

Charge redistribution at graphene/dielectric interfaces is predicated upon the relative positioning of the graphene Fermi level and the charge neutralization level of the dielectric. The authors present an angle-resolved near-edge x-ray absorption fine structure (NEXAFS) spectroscopy investigation of single-layered graphene transferred to 300 nm SiO2/Si with subsequent deposition of ultrathin high-κ dielectric layers to form graphene/dielectric interfaces. The authors’ NEXAFS studies indicate the appearance of a distinct pre-edge absorption for graphene/HfO2 heterostructures (but not for comparable TiO2 and ZrO2 constructs). The hole doping of graphene with substantial redistribution of electron density to the interfacial region is proposed as the origin of the pre-edge feature as electron depletion renders part of the initially occupied density of states accessible for observation via NEXAFS spectroscopy. The spectral assignment is validated by calculating the NEXAFS spectra of electron- and hole-doped graphene using density functional theory. In contrast, a similarly sputtered metallic TiN layer shows substantial covalent interfacial hybridization with graphene.

Substrate-assisted nucleation of ultra-thin dielectric layers on graphene by atomic layer deposition

We report on a large improvement in the wetting of Al2O3 thin films grown by un-seeded atomic layer deposition on monolayer graphene, without creating point defects. This enhanced wetting is achieved by greatly increasing the nucleation density through the use of polar traps induced on the graphene surface by an underlying metallic substrate. The resulting Al2O3/graphene stack is then transferred to SiO2 by standard methods.

On the alleviation of Fermi-level pinning by ultrathin insulator layers in Schottky contacts

With a few exceptions, metal-semiconductor or Schottky contacts are rectifying. Intimate n-Ge Schottky contacts are the most extreme example in that their barrier heights are almost independent of the metal used. Such behavior is characterized as pinning of the Fermi level. Quite recently, ultrathin insulator layers placed between the metal and the semiconductor were found to lower the barrier heights of Schottky contacts and to increase their dependence on the metals used. In this way ohmic behavior was achieved without alloying. The barrier heights of intimate Schottky contacts and the valence-band offsets of heterostructures are well described by the intrinsic interface-induced gap states (IFIGS). Insulators fit in this concept because they are large-gap semiconductors. This article demonstrates that the IFIGS concept also explains the experimentally observed alleviation of the Fermi-level pinning or, as it is also addressed, the Fermi-level depinning in metal-ultrathin insulator-semiconductor or MUTIS structures. Their barrier heights are determined by the IFIGS branch-point energy of the semiconductor and the dependence of the barrier heights of the insulator Schottky contacts on the metals used. Furthermore, saturation of the semiconductor dangling bonds by, for example, sulfur or hydrogen adatoms prior to the deposition of the metals also reduces or increases the barrier heights of Schottky contacts irrespective of the metals applied. In other words, no alleviation of the Fermi-level pinning or depinning occurs. These modifications of the barrier heights are explained by the partial ionic character of the covalent bonds between the adatoms and the semiconductor atoms at the interface, i.e., by an extrinsic electric-dipole layer.

Mixed self-assembled monolayer of molecules with dipolar and acceptor character—Influence on hysteresis and threshold voltage in organic thin-film transistors

In this report, we investigate the impact of the molecular dipole moment and redox active head groups (C60) in pure and mixed self-assembled monolayers (SAMs), which serve as an ultra-thin hybrid dielectric layer in low-voltage operating organic thin-film transistors. We show that the dipole of the SAM-forming molecules affects the threshold voltage, while the concentration of redox-active C60 moieties determines the hysteresis in devices with α,α′-dihexyl-sexithiophene and pentacene as organic semiconductors.

Investigation of the band offsets caused by thin Al2O3 layers in HfO2 based Si metal oxide semiconductor devices

Ultrathin dielectric capping layers are a prominent route for threshold voltage control in advanced Si devices. In this work the position of an Al2O3 layer inside a HfO2-based stack is systematically varied and investigated following a low and a high temperature anneal. Electrical results are compared with a sub-nanometer resolution materials characterization, showing a diffusion of Al to the bottom HfO2 interface. A correlation is found between the presence of Al at the bottom interface and a flatband voltage increase. Based on these findings, we propose to use the position of the Al2O3 for fine-tuning the threshold voltage.

The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.

A Strategy for the Maximum Fluorescence Enhancement Based on Tetrahedral Amorphous Carbon-Coated Metal Substrates

Recently metal-enhanced fluorescence (MEF) has been reported. However, the bare metal would always quench the emission if the separation between the fluorophore and metal is very close. In order to get maximum fluorescence enhancement, the key point is to allow the maximum local electric field of plasmonic substrate at the interface to be used, and at the same time the quenching should be efficiently reduced. We demonstrate for the first time that by coating with an ultrathin dielectric layer of tetrahedral amorphous carbon (ta-C), an optically transparent material in the visible, the metal nanostructures can be used to realize the maximum enhancement in MEF. This result can be attributed to the well control of two competitive mechanisms of the local field enhancement and quenching. It is found that a 10 A ta-C layer can modify plasmon resonance of the metal to produce a higher local electric field than uncoated metal and can also reduce the quenching. The coated metal substrate has higher mechanical stab...

Effects of vacuum ultraviolet and ultraviolet irradiation on ultrathin hafnium-oxide dielectric layers on (100)Si as measured with electron-spin resonance

The effects of vacuum ultraviolet (VUV) (7.2 eV) and UV (4.9 eV) irradiation on hafnium-oxide dielectric layers were studied with electron-spin resonance to detect defect states. Silicon dangling-bond defects (Pb centers) and positively charged oxygen vacancies (E′ centers) were detected with g-factor fitting. VUV irradiation increases the level of Pb states, while UV decreases the level of Pb states but increases the level of E′ states significantly. Rapid thermal annealing appears to mitigate these effects. Absolute values of the defect-state concentrations are presented.

Reflection characterization of anisotropic ultrathin dielectric films on absorbing isotropic substrates

The reflection of linearly polarized light from an ultrathin anisotropic dielectric film on isotropic absorbing substrate is investigated analytically in the long-wavelength limit. All analytical results are correlated with the numerical solution of the anisotropic reflection problem on the basis of rigorous electromagnetic theory. Simple analytical approach developed in this work not only gives a physical insight into the reflection problem but also provides a way of estimating the necessary experimental accuracy for optical diagnostics by reflection characteristics. It is shown that obtained expressions are of immediate interest for determining the parameters of anisotropic surface layers. Innovative possibilities for optical diagnostics of anisotropic properties of ultrathin dielectric layers upon absorbing materials are discussed.

Thin Film Metal-Insulator-Metal Junction for Millimeter Wave Detection

In this work, thin film Metal-Insulator-Metal (MIM) tunnel junction based detector using Ni-NiO-Cr has been developed for Millimeter wave (MMW) detection operating at 94 GHz. Arrays of MIM junctions with 1 μm2 contact area and an ultra-thin insulator layer of ~3 nm has been fabricated using e-beam lithography and reactive sputtering techniques. The device characteristics and performance were evaluated by measuring the electrical response of the tunnel junctions. The electrical characteristics of the tunnel junction demonstrated a significant degree of nonlinearity and asymmetry with a sensitivity of 7 V-1 and a MMW response in the μA range tuned by external bias.

Direct low-energy electron beam nanolithography

We describe here an alternative approach to direct low-energy electron beam nanolithography process with no conventional deposition of any resist or self-assembled monolayer. The method is based on direct formation of ultrathin dielectric layer on electron irradiated surface, without generation of structural defects. High-quality electron-induced patterns with lateral resolutions of about 10 nm are demonstrated on SiO 2 surface.

Study of metal oxide-semiconductor capacitors with rf magnetron sputtering TiOx and TiOxNy gate dielectric layer

Metal oxide-semiconductor capacitors with TiOx deposited with different O2 partial pressures (30%, 35%, and 40%) and annealed at 550, 750, and 1000°C were fabricated and characterized. Fourier transform infrared, x-ray near edge spectroscopy, and elipsometry measurements were performed to characterize the TiOx films. TiOxNy films were also obtained by adding nitrogen to the gaseous mixture and physical results were presented. Capacitance-voltage (1MHz) and current-voltage measurements were utilized to obtain the effective dielectric constant, effective oxide thickness, leakage current density, and interface quality. The results show that the obtained TiOx films present a dielectric constant varying from 40 to 170 and a leakage current density (for VG=−1V, for some structures as low as 1nA∕cm2, acceptable for complementary metal oxide semiconductor circuits fabrication), indicating that this material is a viable, in terms of leakage current density, highk substitute for current ultrathin dielectric layers.

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO x ) dielectric layer, deposited with different oxygen partial pressure (30, 35 and 40%) and annealed at 550, 750 and 1000 °C, were fabricated and characterized. Capacitance–voltage and current–voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO x films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of − 1 V, as low as 1 nA/cm 2 for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers.

Photoemission Study of Metal/HfSiON Gate Stack

Chemical bonding features in metal (TiN or Ru)/HfSiON gate stacks and electrical potential changes due to dipoles at the metal/dielectric interfaces have been studied by back-side x-ray photoemission measurements of the samples after wet-chemical removal of Si substrate. The photoemission threshold of the metal gate measured through the ultrathin dielectric layer confirms that the potential change of the gate metals, which is nearly equivalent to the difference in the flat-band voltage shift between capacitors with SiO2 and HfSiON, is caused by electron transfer from the HfSiON layer to the metal gate near the interface. From the recovery in the gate potential induced by oxygen incorporation into HfSiON, oxygen vacancies in the HfSiON layer are likely to be possible origin of the gate potential change. Also, from the experimental fact that the gate potential change becomes significant with decreasing thickness of the interfacial SiO2 layer below 3.5nm in Ru/HfSiON/SiO2 gate stacks, it is suggested that the generation of oxygen vacancies in HfSiON caused by oxidation reaction of Si substrate through ultrathin SiO2 layer plays an important role on the electron transfer near the Ru/HfSiON interface.

Practical realization of dual-gate-oxide technology concept using ultra-shallow nitrogen r.f. plasma implantation with plasma and thermal oxidation

In mixed logic/memory circuits manufactured as a system on chip, two different thicknesses of dielectric layers are required. Simultaneous formation of both layers is possible if oxidation of a silicon layer is preceded by local nitrogen implantation, since the rate of oxidation depends on the nitrogen implantation dose and its profile. Experiments presented in this work show a possibility and an attempt of practical realization of controlling a very thin dielectric layer's thickness by preceding the oxidation with an ultra-shallow nitrogen implantation from r.f. plasma. As opposed to the methods presented in the literature so far, where classical implanters or the ion immersion implantation plasma (IIIP) technique were used for ultra-shallow implantation, our process is performed in a typical PECVD planar plasma reactor. The r.f. plasma nitrogen implantation has been carried out from NH 3 plasma and then immediately followed by the thermal- or plasma-oxidation process. The electrophysical properties of the obtained layers and systems (ultrathin dielectric layer, silicon) were characterized by electrical methods. Results of ellipsometric, XPS and ULE-SIMS measurements are also presented and discussed.