Ultrathin Channel Research Articles

(Invited) Ultra-Low Power III-V-Based Mosfets and Tunneling FETs

CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V MOSFETs and TFETs including the hetero-structures. One strategy to reduce Vdd is to increase Ion of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, III-V/Ge materials are promising. One of the most critical problems for III-V MOSFETs on Si platform is high quality III-V channel formation on Si substrates. As a technology of the III-V channel formation, we are focusing on III-V wafer bonding to Si substrates. We have developed a bonding technology extendable to 300-mm Si wafers, where III-V channels are grown on Si with thick buffers and transferred to Si wafers [1]. The high channel quality with a low defect density has been confirmed from the tight leakage current distribution. By using InGaAs-OI substrates fabricated by wafer bonding, we have demonstrated tri-gate In0.3Ga0.7As (3nm)/InAs (3nm)/In0.3Ga0.7As (3nm)-on-insulator quantum well (QW) MOSFETs [2]. High Ion and suppressed short channel effects have been obtained by the narrow width tri-gate structure and the optimized ultrathin quantum-well channels [2, 3]. Also, the other strategy to reduce Vdd is to realize steep slope devices with low sub-threshold swing (S.S.). Here, TFETs are one of the most promising steep slope devices, which have been regarded as mandatory for future scaled LSIs for ultra-low power and IoT applications [4]. There can be two critical issues to realize high performance TFETs. One issue is the choice of the source/channel materials enabling to increase tunneling current. Thus, semiconductors such as Ge and III-V are expected as suitable materials with small and/or direct band gap for enhancing Ion of TFETs. In addition, source/channel junctions composed of type-II hetero-structures are effective in boosting the TFET performance without increase in the junction leakage current. Also, the second critical issue is the defect-less source tunnel junction formation with the optimum source concentration and the steep source impurity profile, which leads to sufficiently thin tunneling width and resulting high tunneling current with minimized leakage currents. From this viewpoint, the technologies to form the source tunnel junctions are of paramount importance. The source regions of n-InGaAs TFETs were formed by selective diffusion from Z-doped SOG [5], which can automatically realize the steep Zn profile, thanks to the concentration-dependent diffusion constant of Zn in InGaAs. We have combined this source with InGaAs quantum well (QW) channels, resulting in enhanced Ion and suppressed Ioff of n-TFETs [6, 7]. The minimum S.S. of 54 mV/dec. has been obtained at room temperature for the In0.53Ga0.47As /In0.67Ga0.33As/In0.53Ga0.47As QW n-TFETs having W/HfO2/Al2O3 gate stacks with CET of 1.4 nm. Type-II hetero-structure GaAsSb/InGaAs TFETs are also regarding as one of the most promising material systems for TFETs. We experimentally observed the operation of vertical n-TFETs with InGaAs channels and GaAsSb sources doped in an in-situ manner during the epitaxial growth, which also realized the steep impurity profiles [8]. While high leakage current in the source junctions degrades the performance at 300 K, TFETs with the high GaAsSb source doping concentration of 1x1020 cm-3 have exhibited the Ion/Ioff ratio of 109, the minimum SS of ~30 mV/dec. and Ion of ~4 mA/mm at 20 K. We have also confirmed the operation of GaAsSb/InGaAs n-TFETs on a Si wafer, which was fabricated by direct wafer bonding [4]. This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT. The authors would like to thank Drs. M. Yokoyama, O. Ichikawa, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, Drs. M. Mitsuhara, H. Sugiyama, Hoshi and H. Yokoyama in NTT for their collaborations.

Observation of Wigner crystal phase and ripplon-limited mobility behavior in monolayer CVD MoS2 with grain boundary

Two-dimensional electron gas (2DEG) is crucial in condensed matter physics and is present on the surface of liquid helium and at the interface of semiconductors. Monolayer MoS2 of 2D materials also contains 2DEG in an atomic layer as a field effect transistor (FET) ultrathin channel. In this study, we synthesized double triangular MoS2 through a chemical vapor deposition method to obtain grain boundaries for forming a ripple structure in the FET channel. When the temperature was higher than approximately 175 K, the temperature dependence of the electron mobility μ was consistent with those in previous experiments and theoretical predictions. When the temperature was lower than approximately 175 K, the mobility behavior decreased with the temperature; this finding was also consistent with that of the previous experiments. We are the first research group to explain the decreasing mobility behavior by using the Wigner crystal phase and to discover the temperature independence of ripplon-limited mobility behavior at lower temperatures. Although these mobility behaviors have been studied on the surface of liquid helium through theories and experiments, they have not been previously analyzed in 2D materials and semiconductors. We are the first research group to report the similar temperature-dependent mobility behavior of the surface of liquid helium and the monolayer MoS2.

Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or $\Delta {E}_{v}$ ) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high- $\kappa$ /metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage ( ${V}_{{\text {th}}}$ ) adjustment. For a high reliability, modeling of the mobility ( $\mu$ ) and saturation velocity ( ${v}_{{\text {sat}}}$ ) is carried out for different Ge fractions ( ${x}$ ). The Eg and VBO are also determined for different ${x}$ from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to Lg = 5 nm. At Lg of 5 nm with a driving voltage (VDD) of −0.5 V, a current gain cutoff frequency (fT) = 368.88 GHz, dynamic power = 0.055 fJ/ $\mu \text{m}$ , and an intrinsic delay $(\tau) = 0.37$ ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

High-gain narrow-band slotted antenna based on ENZ SIW structure

The development of a slotted substrate integrated waveguide antenna with an epsilon near zero (ENZ) material is presented. Here, an ENZ waveguide structure is used in the design. The ENZ material is used to realize unconventional tunneling of electromagnetic energy with ultra-thin subwavelength channels and it is considered to attain a highly directive narrow band antenna. The effect of the various parameters of the antenna is studied by simulation. A prototype is fabricated and the measurement results are compared with the simulated values.

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

SiGe Heterojunction FinFET Towards Tera-Hertz Applications

In this work, a novel structure FinFET having an ultra-thin SiGe shell channel forming a heterojunction with Si core is proposed and characterized, with an emphasis on high-speed operation capability in the tera-hertz (THz) regime, by 3-dimensional (3-D) device simulation. The proposed device is operated in the p-type enhancement mode and the ultra-thin SiGe channel confines the mobile holes very effectively by the help of the valence band offset (VBO) between SiGe channel and Si core. The simulations with multiple drift and diffusion models and quantum mechanical models for higher accuracy allow to predict the minimum channel thickness and Ge content of 2 nm and 40%, respectively, for suppressing the hole leakage outflowing over the VBO. Also, scalability was checked down to 5 nm for achieving the upcoming logic technology nodes. Cut-off frequency (f T ) and maximum oscillation frequency (fmax) are obtained to be 240 GHz and 1.04 THz at a low drive voltage as −0.7 V, respectively.

Tunneling Transistors Based on MoS2/MoTe2 Van der Waals Heterostructures

2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control. TMDs are especially well suited for tunneling field-effect transistors (TFETs) due to their low-dielectric constant and their promise of atomically sharp and self-passivated interfaces. Here, we experimentally demonstrate band-to-band tunneling (BTBT) in Van der Waals heterostructures formed by MoS2 and MoTe2. Density functional theory simulations of the band structure show our MoS2-MoTe2 heterojunctions have a staggered band alignment, which boosts BTBT compared to a homojunction configuration. Low-temperature measurements and electrostatic simulations provide understanding toward the role of Schottky contacts and the material thickness on device performance. Negative differential transconductance-based devices were also demonstrated using a different device architecture. This paper provides the prerequisites and challenges required to overcome at the contact region to achieve a steep subthreshold slope and high ON-currents with 2-D-based TFETs.

Understanding contact gating in Schottky barrier transistors from 2D channels

In this article, a novel two-path model is proposed to quantitatively explain sub-threshold characteristics of back-gated Schottky barrier FETs (SB-FETs) from 2D channel materials. The model integrates the “conventional” model for SB-FETs with the phenomenon of contact gating – an effect that significantly affects the carrier injection from the source electrode in back-gated field effect transistors. The two-path model is validated by a careful comparison with experimental characteristics obtained from a large number of back-gated WSe2 devices with various channel thicknesses. Our findings are believed to be of critical importance for the quantitative analysis of many three-terminal devices with ultrathin body channels.

Feasibility of ultra-sensitive 2D layered Hall elements

A Hall effect sensor is an analog transducer that detects a magnetic flux. The general requirements for its high magnetic sensitivity in conventional semiconductors are high carrier mobility and ultra-thin conduction channel in the material’s and the device’s point of view. Recently, graphene Hall elements (GHEs) that satisfy those conditions have been demonstrated with a current-normalized magnetic sensitivity (SI) superior to that of Si-based Hall sensors. Nevertheless, the feasibility of Hall elements based on an atomically thin monolayer transition metal dichalcogenide (TMD) system has not been studied thus far, although such a system would further enable a largely suppressed 2D carrier density. Herein, we show the strategy how to achieve the highest possible SI in a TMD-based Hall element in terms of the device structure as well as the operating bias condition. A monolayer molybdenum disulfide Hall element (MHE) on a hexagonal boron nitride (h-BN) thin film was fabricated, and the best bias conditions were selected based on the analytical model for zero-field transconductance data. Finally, the maximum SI of MHE/h-BN was found to be ~3000 V/AT. This work sheds light on the feasibility of TMD-based Hall element systems.

Dual-Band Filter Inspired by ENZ Waveguide

This letter presents a novel design of the third-order dual-band filter operating in the frequency band 10–15 GHz. The filter consists of two rectangular cavities filled with foam dielectric and connected by an ultrathin waveguide channel, which mimics the epsilon-near-zero metamaterial. Each resonator is designed to support two propagating modes—one per each passband. By changing the filter dimensions for which we have derived analytical expressions, it is possible to change the center frequency of both passbands, their fractional bandwidths, and the position of the transmission zero between passbands.

Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects

In this work, analytical models of subthreshold current and subthreshold swing of short channel ultra-thin double gate-all-around (DGAA) MOSFETs including quantum confinement effects have been proposed. The subthreshold current model is presented using Pao-Sah's double integration formula accounting both drift and diffusion components of the current. Quantum effects arising due to 2-D carrier confinement are incorporated in the model to consider the effective carrier density reduction in ultra-thin channel region. A detailed analysis of charge density calculation using density of states (DOS) method is also done. Further, the virtual-cathode potential has been utilised to model the subthreshold swing of the device. The effect of device design parameters like channel thickness, oxide thickness, gate length etc. on subthreshold characteristics has been extensively studied. The model results have been verified by comparing it with the numerical simulation data obtained from 3D device simulator Visual TCAD of Cogenda Int.

High Performance and Low power Monolithic Three-Dimensional Sub-50\u2009nm Poly Si Thin film transistor (TFTs) Circuits

Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

Characterization of Scaling in Ultra-Thin Poly-Si and Analysis of the Scaling Limit of Thin Film Thickness

Ultra-thin poly-Si channel has been widely studied and has already been adopted commercially by semiconductor manufacturers due to its short channel effect suppression and sub-threshold swing improvement. It is well known that the threshold voltage, VTH, increase as the poly-Si thickness, ts, is scaled below 10nm, due to quantum-mechanical (QM) effects. Although experiment results of VTH demonstrated identical behavior of increasing as ts was scaled, but the measured absolute VTH show significantly larger value than the expectation. The major problem of abrupt VTH increase is that it degenerate VTH distribution, which would cancel out merits of ultra-thin poly-Si device on high speed performance. Simulation results show the abrupt VTH increase is caused by a combined effect of bulk and front/back interface trap charges. As scaled down, yet the bulk trap density decrease, VTH is increased as it is overturned by front and back interface trap charge effects. Compared to front interface trap charges, back interface trap charges have larger influence on VTH. Since device with ts below 10nm is fully depleted before the gate voltage reaches VTH, the additional electric field formed across the poly-Si channel parallel shifts the band downwards. So the more parallel shifted the band is, the more additional portion of the front and back interface is filled with negative charge. As a result back interface charges increase VTH. The closer it gets to the channel, greater the influence become. It is quite clear why back interface trap charges contribute more to the VTH, compared with front interface trap charges. The simulation results considering bulk and front/back interface trap effects showed a good match experiment results. Considering the abrupt VTH increase and variation of poly-Si deposition process, the fundamental criterion of poly-Si thickness scaling limit should be no lower than 5nm.

Room-temperature field effect transistors with metallic ultrathin TiN-based channel prepared by atomic layer delta doping and deposition

Metallic channel transistors have been proposed as the candidate for sub-10 nm technology node. However, the conductivity modulation in metallic channels can only be observed at low temperatures usually below 100 K. In this study, room-temperature field effect and modulation of the channel resistance was achieved in the metallic channel transistors, in which the oxygen-doped TiN ultrathin-body channels were prepared by the atomic layer delta doping and deposition (AL3D) with precise control of the channel thickness and electron concentration. The decrease of channel thickness leads to the reduction in electron concentration and the blue shift of absorption spectrum, which can be explained by the onset of quantum confinement effect. The increase of oxygen incorporation results in the increase of interband gap energy, also giving rise to the decrease in electron concentration and the blue shift of absorption spectrum. Because of the significant decrease in electron concentration, the screening effect was greatly suppressed in the metallic channel. Therefore, the channel modulation by the gate electric field was achieved at room temperature due to the quantum confinement and suppressed screening effect with the thickness down to 4.8 nm and the oxygen content up to 35% in the oxygen-doped TiN ultrathin-body channel.

Ultra-high aspect ratio poly-Si FinFET using an improved spacer formation technique

An improved spacer formation technique was proposed and developed to fabricate poly-Si fin field-effect transistors (FinFETs) with an ultra-high aspect ratio. The as-demonstrated FinFETs have a fin channel with a width and height of 22 nm and 230 nm, respectively, corresponding to an aspect ratio of 10.5. The electrical and temperature properties of the FinFETs are described in detail in this paper. The poly-Si FinFETs exhibit a steep subthreshold swing (196 mV/dec), a low leakage current (∼10−14 A), a high on/off current ratio (2.2 × 107 at VDS = 0.1 V), and a low drain-induced barrier lowering effect (0.28 V). The excellent switching characteristics are attributed to the ultrathin channel body and the multi-gate structure combined with high-k Al2O3 dielectric. Furthermore, the electron field-effective mobility increases as the temperature increases. An analytical fitting model was derived and was utilized to account for this phenomenon. The fitting results indicate that the positive temperature coefficient originates from the grain boundary-controlled mechanism in the low gate voltage regime.

Nitride Dielectric Environments to Suppress Surface Optical Phonon Dominated Scattering in High‐Performance Multilayer MoS2 FETs

The ultrathin channel in 2D semiconductors, although playing host to several interesting properties, also renders strong interactions (scattering) of charge carriers with the surrounding medium. The over‐arching dominance of surface (interfacial) optical phonons in 2D charge transport and engineering ideal nitride‐based dielectric environments for large performance gains is reported. Charge transport in MoS2 field effect transistors (FETs) fabricated on three conventional substrates, SiO2, Al2O3, and HfO2, is contrasted with a newly introduced, CMOS‐compatible nitride‐based dielectric: aluminum nitride (AlN) by employing semi‐classical models which account for charged impurity, surface optical phonon, and intrinsic phonon scattering. Unlike previous reports focused on charge impurity scattering, this work presents a new paradigm of utilizing high optical phonon energies intrinsic to “stiff” nitride bonds. This results in substantially lower surface optical phonon scattering in 2D FETs which directly influences peak field effect (FE) mobility, high field mobility degradation, and temperature‐dependent mobility. Leveraging on these insights, high‐performance sulfur‐passivated MoS2 FETs with an optimum all‐nitride environment (hexagonal boron nitride/MoS2/AlN) are demonstrated with FE mobility up to 72.8 cm2 V−1 s−1. This work is envisioned to address important issues in design of dielectric environments for a host of applications based on 2D materials.

Epitaxial growth of In-rich InGaN on yttria-stabilized zirconia and its application to metal–insulator–semiconductor field-effect transistors

We grew In-rich InxGa1-xN films on yttria-stabilized zirconia (YSZ) substrates at low temperatures by pulsed sputtering deposition. It was found that single-crystal InxGa1-xN (0.63 ≤ x ≤ 0.82) films can be prepared without significant compositional fluctuations at growth temperatures below 500 °C. It was also found that the electrical properties of InGaN are strongly dependent on In composition, growth temperature, and film polarity. N-channel operation of the metal–insulator–semiconductor field-effect transistor (MISFET) with an ultrathin InGaN channel on the YSZ substrates was successfully demonstrated. These results indicate that an InGaN-based MISFET is a promising device for next-generation high-speed electronics.

Non-volatile memory based on atomic crystals

The space and data-exchanging rate and other factors of storage, calculation and communication in the multi-functional low-power chips have become the bottlenecks of the development of integrated circuits. The ultralow power consumption of single-bit erasing/writing, the ultra-small device size, fast operation time and non-volatility are indispensable for high-density and high-speed storage in the future system architecture to satisfy the needs for big data exchanging in the core. The future storage technology consists of employing devices with new principles, such as controlling of electron transition and ionic migration superseding the electron transport, adopting new materials to lower the power consumption and introducing new 3D-stack technology to increase the density. This review focuses on the application of new materials in the non-volatile storage technology, especially the two-dimensional atomic crystals. Two-dimensional atomic crystals have some prominent properties, such as high electron mobility, ultimate ultrathin channel and ultralow surface states with an intrinsic thickness of 0.6‒1.2 nm and abundant band structure, which provide an excellent solution for future storage technology. And they have enormous potential to further scale down to increase the integration level and improve stability, expand the application scenarios and develop new memory devices and they are a new method to break through the bottlenecks of power consumption and integrated level of memories.

Ultrathin LiFePO4 nanosheets self-assembled with reduced graphene oxide applied in high rate lithium ion batteries for energy storage

Liquid-phase ultrasonic exfoliation approach was applied to acquire ultrathin lithium iron (II) phosphate (LiFePO4) nanosheets (LFP-NS) with the thickness of only ∼15nm. The LFP-NS were then self-assembly with graphene oxide (GO) with amido bonds. Ultrashort diffusion pathways to lithium ions (Li+) could be achieved with high percentage of (010) facets exposed to LFP-NS, which reduced the diffusion distance for Li+ along the [010] direction effectively. In addition, the reduced graphene oxide (rGO) firmly adhered to the surface of LFP-NS by self-assemble method after sintering, which formed an excellent conductive network and facilitate electron transportation. The ultrathin diffusion channels into Li+ and tight conductive network resulting in an excellent high rate discharging performance, e.g. up to 102mAhg−1 at 30C, while discharge capacity retention can reach to 93.4% at 20C after 500 cycles. This kind of composite was an ideal cathode material used in high rate lithium ion batteries.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in IOFF of ∼ 9 × 10−16 A/μm, ION of ∼20 μA/μm, ION/IOFF of ∼2 × 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.