Abstract
Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
Highlights
Integration of complementary metal oxide semiconductor (CMOS) circuits comprising both p- and n-type thin-film transistors (TFTs) are basic building blocks for complex integrated circuits toward system-on-chip and other electronic applications
We demonstrated a polycrystalline Si thin-film transistors (TFTs) based on the monolithic 3D-IC sequential integration (3DSI) method to achieve a low-cost fabrication process with a low thermal budget for the monolithic 3D-IC application
Laser crystallization (LC) is the most commonly used to produce a poly-Si film with a low defect density and a higher field effect mobility, which was utilized to achieve the poly-Si film from the crystallization of the a-Si film in our study[15]
Summary
Integration of complementary metal oxide semiconductor (CMOS) circuits comprising both p- and n-type TFTs are basic building blocks for complex integrated circuits toward system-on-chip and other electronic applications To achieve this goal, heterogeneously integrated three-dimensional integrated circuit (3DIC) technology is the best candidate to achieve this target to realize device integration with high performance, multifunction, wide bandwidths and low power consumption. On how to reduce thermal impact of device fabrication to avoid degradation of pre-existing devices, resembling back-end process In this regard, we demonstrated a polycrystalline Si thin-film transistors (TFTs) based on the monolithic 3D-IC sequential integration (3DSI) method to achieve a low-cost fabrication process with a low thermal budget for the monolithic 3D-IC application. The advanced 3D architecture with a closely spaced interlevel dielectric (ILD) enables high-performance stackable MOSFETs and SRAM for the power-saving internet of things (IoT)/mobile products on low cost or flexible substrate
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