Ultra-short Channel Research Articles

Two-Dimensional Vertical Transistor with One-Dimensional van der Waals Contact.

Two-dimensional (2D) materials enable vertical field effect transistors (VFETs), which provide an alternative path for scaling down the channels of transistors. The challenge is the short channel effect when the thickness of the 2D channel decreases to ∼10 nm. Here, we show that a VFET with an ultrashort channel can be accomplished by employing a semimetal carbon nanotube (CNT) as a 1D van der Waals (vdW) contact. The CNT-VFETs with 5-10 nm MoS2 channels exhibit high on/off ratios exceeding 105, low subthreshold swing values of 160-120 mV/dec, and high current densities over 104 A/cm2. Such a switch even works with an ∼ 3.4 nm thick channel. The excellent comprehensive performance can be ascribed to the reduced short channel effect as the sub-2 nm CNT contact has weaker electrostatic screening to the gate, a reduced Fermi level pinning effect, and a highly tunable barrier. The VFETs with 1D vdW contacts hold great promise for ultrascaled transistors and are prospective in future nanoelectronics and nano-optoelectronics.

Large-scale sub-5-nm vertical transistors by van der Waals integration

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

Harnessing Holey MXene/Graphene Oxide Heterostructure to Maximize Ion Channels in Lamellar Film for High-Performance Capacitive Deionization.

2D Ti3C2Tx MXene-based film electrodes with metallic conductivity and high pseudo-capacitance are of considerable interest in cutting-edge research of capacitive deionization (CDI). Further advancement in practical use is however impeded by their intrinsic limitations, e.g., tortuous ion diffusion pathway of layered stacking, vulnerable chemical stability, and swelling-prone nature of hydrophilic MXene nanosheet in aqueous environment. Herein, a nanoporous 2D/2D heterostructure strategy is established to leverage both merits of holey MXene (HMX) and holey graphene oxide (HGO) nanosheets, which optimize ion transport shortcuts, alleviate common restacking issues, and improve film's mechanical and chemical stability. In this design, the nanosized in-plane holes in both handpicked building blocks build up ion diffusion shortcuts in the composite laminates to accelerate the transport and storage of ions. As a direct outcome, the HMX/rHGO films exhibit remarkable desalination capacity of 57.91mg g-1 and long-term stability in 500mgL-1 NaCl solution at 1.2V. Moreover, molecular dynamics simulations and ex situ wide angle X-ray scattering jointly demonstrate that the conductive 2D/2D networks and ultra-short ion diffusion channels play critical roles in the ion intercalation/deintercalation process of HMX/rHGO films. The study paves an alternative design concept of freestanding CDI electrodes with superior ion transport efficiency.

P‐22: Fabrication of Ultra Short Channel Oxide Thin Film Transistors

By utilizing flat display panel manufacturing equipment and innovative techniques, we have successfully developed short channel Top‐gate amorphous InGaZnO4 thin‐film transistors (TG a‐IGZO TFTs) at Gen4.5. Despite the challenge of facing issues with the lateral diffusion of hydrogen during process and short channel effects, we managed to optimize the uniformity and drain‐induced barrier lowering with the novel structure of TFTs. After optimizing the device structure, we have achieved short channel TFTs with channel length of 1.3um, Vth of ‐ 0.03V, mobility of 9.77 cm2 /Vs, and DIBL of 29mV/V, and successfully make a demo of 7.1inch miniLED with the ultra short channel TFTs.

Performance assessment of monolayer Black Phosphorus DG-JLFET

Two-dimensional materials are very promising for ultra-short channel future devices. This paper investigates, for the first time, the viability of the junction less transistors based on 2-D materials for future state-of-the-art technology nodes. Specifically, we investigate the performance of a Junction less monolayer black phosphorus (BP) FET (JLFET) with 12nm gate length using ab initio quantum transport simulations. The electrostatic control mechanism of the device and various intrinsic static and dynamic characteristics of the device are studied. The results reveal that BP JLFET performance can fulfill the benchmark requirement of International Roadmap for Devices and Systems (IRDS 2021) for 2028 in terms of HP and HD applications. Therefore, JLFET based on 2D materials can be a promising alternative for nano scale future device applications.

Recent Experimental Breakthroughs on 2D Transistors: Approaching the Theoretical Limit

AbstractSince Si‐based Moore's law is physically limited, 2D semiconductors are proposed as successors to continue shrinking the transistor size for more Moore electronics. However, limited by experimental technology bottlenecks, the theoretical predicted superiorities of the 2D transistors over the state‐of‐the‐art Si transistors have been lacking concrete evidence for a decade. In this review, recent exciting experimental breakthroughs for 2D transistors are presented, including gate length miniaturization to a sub‐1 nm limit, electrode contact optimization to the resistance quantum limit, high‐quality dielectric fabrication with an equivalent oxide thickness to sub‐0.5 nm, novel architecture form (2D fin field‐effect transistor), and back‐end‐of‐line integration of directly grown 2D materials on Si complementary metal‐oxide‐semiconductor circuits. Remarkably, an ultrashort channel, Ohmic contact, ballistic transport, and ultrathin dielectric layer are simultaneously satisfied in the 2D InSe transistor, and device performances approaching the theoretical limit are observed. The measured key figures of merit of the ideal 2D InSe transistor are comparable to or even surpass those of the Si transistors. Finally, the challenges and outlook on more Moore electronics based on 2D transistors are highlighted.

Ultrashort channel MoSe2 transistors with selenium atoms replaced at the interface: first-principles quantum-transport study

Realizing n- and p-type transition metal dichalcogenide (TMD)-based field-effect transistors for nanoscale complementary metal oxide semiconductor (CMOS) applications remains challenging owing to undesirable contact resistance. Quantumtransport calculations were performed by replacing single-sided Se atoms of TMD near the interface with As or Br atoms to further improve the contact resistance. Here, partial selenium replacement produced a novel interface with a segment of metamaterial MoSeX (Pt/MoSeX/MoSe2; X = As, Br). Such stable metamaterials exhibit semi-metallicity, and the contact resistance can be thus lowered. Our findings provide insights into the potential of MoSe2-based nano-CMOS logic devices.

Lateral junctions of transition metal dichalcogenides as ballistic channels for straintronic applications

In the context of advanced nanoelectronics, two-dimensional semiconductors such as transition metal dichalcogenides (TMDs) are gaining considerable interest due to their ultimate thinness, clean surface and high carrier mobility. The engineering prospects offered by those materials are further enlarged by the recent realization of atomically sharp TMD-based lateral junctions, whose electronic properties are governed by strain effects arising from the constituents lattice mismatch. Although most theoretical studies considered only misfit strain, first-principles simulations are employed here to investigate the transport properties under external deformation of a three-terminal device constructed from a MoS2/WSe2/MoS2 junction. Large modulation of the current is reported owing to the change in band offset, illustrating the importance of strain on the p–n junction characteristics. The device operation is demonstrated for both local and global deformations, even for ultra-short channels, suggesting potential applications for ultra-thin body straintronics.

Toward grouped-reservoir computing: organic neuromorphic vertical transistor with distributed reservoir states for efficient recognition and prediction

Reservoir computing has attracted considerable attention due to its low training cost. However, existing neuromorphic hardware, focusing mainly on shallow-reservoir computing, faces challenges in providing adequate spatial and temporal scales characteristic for effective computing. Here, we report an ultra-short channel organic neuromorphic vertical transistor with distributed reservoir states. The carrier dynamics used to map signals are enriched by coupled multivariate physics mechanisms, while the vertical architecture employed greatly increases the feedback intensity of the device. Consequently, the device as a reservoir, effectively mapping sequential signals into distributed reservoir state space with 1152 reservoir states, and the range ratio of temporal and spatial characteristics can simultaneously reach 2640 and 650, respectively. The grouped-reservoir computing based on the device can simultaneously adapt to different spatiotemporal task, achieving recognition accuracy over 94% and prediction correlation over 95%. This work proposes a new strategy for developing high-performance reservoir computing networks.

Tribotronic Vertical Field‐Effect Transistor Based on van der Waals Heterostructures

AbstractGraphene has attracted considerable interest for next‐generation electronics. However, the absence of natural bandgap has limited the current on/off ratio of graphene‐based transistors. Vertical integration of 2D heterostructures offers a promising approach to address this challenge, enabling high‐current‐density vertical field‐effect transistor (VFET) with large on/off ratio. Here, a triboelectric potential‐powered VFET with a vertical stacked graphene/MoS2 heterostructure and a sliding‐mode triboelectric nanogenerator (TENG) coupled with gate dielectrics are proposed. The tribotronic VFET has an ultrashort channel length in vertical direction, exhibiting excellent current driving capability with an ultrahigh on‐state current density of 950 A cm−2 and a good current on/off ratio of 630. It also demonstrates reconfigurable diode behavior with a rectification ratio over 102. Temperature‐dependent studies are applied to tribotronic devices for the first time, indicating an effective modulation on the Schottky barrier height of 150 meV by the triboelectric potential. A green LED pixel is driven by the tribotronic VFET as a demonstration to work as a tactile interactive light‐emitting device. The demonstrated tribotronic vertical device offers a promising strategy for integrating various 2D layered materials with TENG in vertical direction, enabling 3D integration of low‐power and interactive devices for next‐generation electronics.

A vertically-stacked MXene/rGO composite membrane for highly efficient H2/CO2 separation.

A vertically-stacked MXene/rGO composite membrane with ultrashort transport channels is reported here, which demonstrated outstanding molecular sieving, i.e., H2/CO2 selectivity of up to 83 together with high H2 permeance of 2.7 × 10-7 mol m-2 s-1 Pa-1 at 120 °C, highlighting its applicability for H2/CO2 separation in CO2 capture and sequestration.

Ultra-thin vertical tft photosensor and photosynapse based on au-doped- graphene under transition metal selenide reaction

The development of artificial photosensitive synapses with high sensitivity and biomimetic properties that combine innovative concepts and neuromorphic architectures is crucial to achieving highly integrated and flexible intelligent visual systems. Recently, graphene heterostructure-based photosensitive synaptic transistors have been extensively studied for this purpose. However, compared to traditional transistors, vertical structure thin film transistors (VTFTs) with ultra-short channels and advantages, such as high integration, have yet to be investigated in photosensitive synapses. Here, we report an ultra-thin VTFT featuring a graphene/WxSex–1 van der Waals heterostructure that combines photonic and neuromorphic elements. We demonstrate a VTFT in which the channel layer is formed by covalently bonded WxSex–1 nanomaterials produced by introducing Se atoms on the surface of a tungsten metal thin film deposited via radio-frequency sputtering. This structure successfully simulated the main synaptic function, exhibited photosensitive synaptic responses to ultraviolet (λ = 365 nm) light, and demonstrated highly reliable electrical performance. Furthermore, the incorporation of gold nanoparticles changed the photosensitive synaptic response properties of the graphene/WxSex–1 heterostructure from excitatory to inhibitory, showing a responsivity of about ∼14 A W–1, which was attributed to the heterojunction interface resonant effects and efficient charge transfer induced by localized surface plasmons. This further enabled optical artificial synaptic applications while operating with low voltage spikes and low light intensity. This work provides a novel strategy for integrating and developing biological and nano-electronic systems.

High-sensitive two-dimensional PbI2 photodetector with ultrashort channel

High-sensitive two-dimensional PbI2 photodetector with ultrashort channel

Scaling of MoS2 Transistors and Inverters to Sub-10 nm Channel Length with High Performance

Two-dimensional (2D) semiconductors such as monolayer molybdenum disulfide (MoS2) are promising building blocks for ultrascaled field effect transistors (FETs), benefiting from their atomic thickness, dangling-bond-free flat surface, and excellent gate controllability. However, despite great prospects, the fabrication of 2D ultrashort channel FETs with high performance and uniformity remains a challenge. Here, we report a self-encapsulated heterostructure undercut technique for the fabrication of sub-10 nm channel length MoS2 FETs. The fabricated 9 nm channel MoS2 FETs exhibit superior performances compared with sub-15 nm channel length including the competitive on-state current density of 734/433 μA/μm at VDS = 2/1 V, record-low DIBL of ∼50 mV/V, and superior on/off ratio of 3 × 107 and low subthreshold swing of ∼100 mV/dec. Furthermore, the ultrashort channel MoS2 FETs fabricated by this new technique show excellent homogeneity. Thanks to this, we scale the monolayer inverter down to sub-10 nm channel length.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Promising ultra-short channel transistors based on OM2S (M = Ga, In) monolayers for high performance and low power consumption.

It is hoped that two-dimensional (2D) semiconductors overcome the short channel effect and continue Moore's law. However, 2D material-based ultra-short channel devices still face the challenge of simultaneously achieving high-performance (HP) and low-power (LP) consumption. Here, we theoretically designed monolayer OM2S (M = Ga, In)-based metal-oxide-semiconductor field-effect transistors (MOSFETs), considering the gate length from 1 to 5 nm, doping concentration and underlap structure. We found that in HP (LP) applications, the on-state current exceeds 1000 (500) μA μm-1 under a 1 nm (2 nm) gate length, surpassing the needs of the International Technology Roadmap for Semiconductors (ITRS) in 2028. The subthreshold swing is close to the Boltzmann tyranny (60 mV dec-1) even as the gate length shrinks to 2 nm. The energy-delay product is two orders lower than 1.02 × 10-28 J s μm-1, indicating extraordinary high-speed manipulation and low-energy expending. Therefore, monolayer OM2S has great application in ultra-short scale devices with HP and LP consumption, and can be taken as a candidate to extend Moore's Law.

Monolithic Tandem Vertical Electrochemical Transistors for Printed Multi-Valued Logic.

Organic electrochemical transistors (OECTs) have recently emerged as a feasible candidate to realize the next generation of printable electronics. Especially, their chemical versatility and the unique redox-based operating principle have provided new possibilities in high-functioning logic circuitry beyond the traditional binary Boolean logic. Here, a simple strategy to electrochemically realize monolithic multi-valued logic transistors is presented, which is one of the most promising branches of transistor technology in the forthcoming era of hyper Moore's law. A vertically stacked heterogeneous dual-channel architecture is introduced with a patterned reference electrode, which enables a facile manifestation of stable and equiprobable ternary logic states with a reduced transistor footprint. The dual-ion-penetration mechanism coupled with ultrashort vertical channel even allows a very-high accessing frequency to multiple logic states reaching over 10MHz. Furthermore, printed arrays of ternary logic gates with full voltage swing within 1V are demonstrated.

All region analytical modeling of 2-D transition metal dichalcogenide FET by considering effect of fringing field and region-wise mobility

In this paper, for the first time an analytical all region model of Transition metal dichalcogenide based FET has been developed to represent the current–voltage characteristics of the device in ultra-short channel regime. Starting from Gauss’s law, Poisson’s equation is formulated and short channel subthreshold current model is developed subsequently. In order to include fringing field effect, the gaussian box is considered for top and bottom oxides along with channel. Next, Velocity saturation model is developed by considering mobile charges due to top-bottom gates and region-wise field dependent mobility in the channel utilizing the drift diffusion approach. Both the models are then unified by finding the natural points of transition from one model to other. The intraband source to drain tunneling has also been incorporated to develop generalized 2-D material based FET model. Veracity of the model has been verified with NEGF simulations for different device parameters and excellent congruence is observed. The effect of the interface trap charge density has also been included in the model and its effects on the transfer characteristics are investigated. • Analytical modeling of I-V characteristics for TMD materials applicable for all channel lengths. • Validation of model with atomistic simulator data for Sub 10 nm channel length. • Effects of double gate and fringing field have been included. • Source to drain tunneling has been included to increase model applicability for any 2D materials.

Self-charging of sprays

The charging of poorly conducting liquids due to flows is a well-known phenomenon, yet the precise charging mechanism is not fully understood. This is especially relevant for sprays, where the spray plume dynamics and maximum distance travelled of a spray dramatically changes for different levels of charging: charging of the droplets makes them repel, thereby preventing drop coalescence and altering the shape of the spray plume. As the charging depends on many factors including the flow and the interactions between the liquid and the nozzle, many models and scaling laws exist in the literature. In this work we focus on perhaps the simplest flow regime, laminar jets created by ultra short channels, and quantify the charging as a function of the different parameters. We present a simple model that collapses all the data for over 4 orders of magnitude difference in streaming currents for various nozzle sizes, flow velocities and surface treatments. We further show that the charging polarity can even be reversed by applying an oppositely charged coating to the nozzle, an important step for any application.

Contact resistance in sub-micron and nanoscale organic thin-film transistors

Two improved methods for evaluating contact resistance in organic thin-film transistors (TFTs) are presented. These methods can be applied to TFTs with any arbitrary geometry and are also suitable for retroactive analysis of current-voltage characteristics. The first method is based on the analysis of the differential conductance of TFTs and in separating the conductivity contributions from the contacts and the channel. This method provides accurate results when the contact resistance is approximately 0.1–10 times the channel resistance. The second method is especially applicable to nanoscale and short channel length TFTs. The minimum value of differential on-resistance as a function of drain bias is used to separate the contributions of the channel and contact resistances at various drain voltages. This method is accurate when the contact resistance is approximately 0.3–10 times the channel resistance, as verified by simulations. It works even when there is no distinct saturation in current-voltage characteristics with increasing drain voltage. Both methods have been applied to experimental data from organic TFTs with channel lengths in the range 10 nm to 5 μm. • Two novel methods of extracting contact resistance in OTFTs are introduced. • Contact resistance of various channel lengths OTFTs are extracted and analyzed. • Effects of contact resistance in short channel pentacene TFTs are discussed. • New design of ultra-short channel TFTs is proposed to improve carrier injection.