Ultra-low Power Dissipation Research Articles

Unlocking High-Performance, Ultra-Low Power van der Waals Photo-Transistors: Toward Back-End-of-Line in-Sensor Machine Vision Applications.

Recent reports on machine learning and machine vision (MV) devices have demonstrated the potential of two-dimensional (2D) materials and devices. Yet, scalable 2D devices are being challenged by contact resistance and Fermi level pinning (FLP), power consumption, and low-cost CMOS compatible lithography processes. To enable CMOS + 2D, it is essential to find a proper lithography strategy that can fulfill these requirements. Here, we explored a modified van der Waals (vdW) deposition lithography and demonstrated a relatively new class of van der Waals field effect transistors (vdW-FETs) based on 2D materials. This lithography strategy enabled us to unlock high-performance devices evident by high current on-off ratio (Ion/Ioff), high turn-on current density (Ion), and weak FLP. We utilized this approach to demonstrate a gate-tunable near-ideal diode using a MoS2/WSe2 heterojunction with an ideality factor of ∼1.65 and current rectification of 102. We finally demonstrated a highly sensitive, scalable, and ultralow power phototransistor using a MoS2/WSe2 vdW-FET for back-end-of-line integration. Our phototransistor exhibited the highest gate-tunable photoresponsivity achieved to date for white light detection with ultralow power dissipation, enabling ultrasensitive optoelectronic applications such as in-sensor MV. Our approach showed the great potential of modified vdW deposition lithography for back-end-of-line CMOS + 2D applications.

Design and Simulation of Reversible Logic Gate Using HCS Macro-Model

—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.

Hydrogel-Gated FETs in Neuromorphic Computing to Mimic Biological Signal: A Review.

Hydrogel-gated synaptic transistors offer unique advantages, including biocompatibility, tunable electrical properties, being biodegradable, and having an ability to mimic biological synaptic plasticity. For processing massive data with ultralow power consumption due to high parallelism and human brain-like processing abilities, synaptic transistors have been widely considered for replacing von Neumann architecture-based traditional computers due to the parting of memory and control units. The crucial components mimic the complex biological signal, synaptic, and sensing systems. Hydrogel, as a gate dielectric, is the key factor for ionotropic devices owing to the excellent stability, ultra-high linearity, and extremely low operating voltage of the biodegradable and biocompatible polymers. Moreover, hydrogel exhibits ionotronic functions through a hybrid circuit of mobile ions and mobile electrons that can easily interface between machines and humans. To determine the high-efficiency neuromorphic chips, the development of synaptic devices based on organic field effect transistors (OFETs) with ultra-low power dissipation and very large-scale integration, including bio-friendly devices, is needed. This review highlights the latest advancements in neuromorphic computing by exploring synaptic transistor developments. Here, we focus on hydrogel-based ionic-gated three-terminal (3T) synaptic devices, their essential components, and their working principle, and summarize the essential neurodegenerative applications published recently. In addition, because hydrogel-gated FETs are the crucial members of neuromorphic devices in terms of cutting-edge synaptic progress and performances, the review will also summarize the biodegradable and biocompatible polymers with which such devices can be implemented. It is expected that neuromorphic devices might provide potential solutions for the future generation of interactive sensation, memory, and computation to facilitate the development of multimodal, large-scale, ultralow-power intelligent systems.

Designing and performance analysis of 7 T CNTFET based novel SRAM cell for IoT application

The selection of the title includes designing of SRAM cell using CNTFET because CNTFET overcomes all the issues coming from CMOS technology beyond the 10nm technology node. With the reduction in channel length, the threshold voltage required for CMOS-based technology increases, and the corresponding off-state current decreases. This can prove to be a significant advancement for the semiconductor industry. With the evolution of the new generation of the technology era, especially beyond 10 nm, CMOS is not able to fulfil all the required conditions, as beyond 10 nm technology node, threshold voltage decreases, and consequently off-state current and leakage power increase. This is the reason that CNTFET can be considered a prominent replacement of CMOS transistor for the designing of SRAM cells with the technology node beyond 10 nm. This designed SRAM cell is applicable for IoT applications because IoT uses a microcontroller and the SRAM cell is used as a data memory in the microcontroller. A Data memory always requires high speed, ultra-low power dissipation, and high stability from the cell. Thus, to fulfil this requirement, performance analysis to identify the problem statement of conventional cells and then to improve their performance based on the findings is essential. This is the reason that the 7 T CNTFET-based SRAM novel cell is introduced, and its performance is going to be further improved so that the designed novel cell becomes compatible with IoT applications. Leakage power and stability factor are the main performance parameters to improve of SRAM cells.

Nanoelectromechanical Control of Spin-Photon Interfaces in a Hybrid Quantum System on Chip.

Color centers (CCs) in nanostructured diamond are promising for optically linked quantum technologies. Scaling to useful applications motivates architectures meeting the following criteria: C1 individual optical addressing of spin qubits; C2 frequency tuning of spin-dependent optical transitions; C3 coherent spin control; C4 active photon routing; C5 scalable manufacturability; and C6 low on-chip power dissipation for cryogenic operations. Here, we introduce an architecture that simultaneously achieves C1-C6. We realize piezoelectric strain control of diamond waveguide-coupled tin vacancy centers with ultralow power dissipation necessary. The DC response of our device allows emitter transition tuning by over 20 GHz, combined with low-power AC control. We show acoustic spin resonance of integrated tin vacancy spins and estimate single-phonon coupling rates over 1 kHz in the resolved sideband regime. Combined with high-speed optical routing, our work opens a path to scalable single-qubit control with optically mediated entangling gates.

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

Novel Slumped SRAM Configuration using QCA Leveraging Differential Voltage Sensing for Enhanced Stability and Efficiency

This paper presents a novel Slumped Static Random-Access Memory (SRAM) configuration utilizing Quantum-dot Cellular Automata (QCA) technology, aimed at achieving enhanced stability and efficiency. Traditional CMOS-based SRAM designs face significant challenges related to power consumption and scalability as technology nodes shrink. QCA, with its potential for ultra-low power dissipation and high-density integration, emerges as a promising alternative. Our proposed SRAM configuration leverages a unique differential voltage sensing mechanism to bolster the stability of the memory cells, particularly under conditions of variability and noise. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration not only improves static noise margin (SNM) but also reduces power consumption and enhances overall readwrite speed. The results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration achieves a static noise margin (SNM) improvement of 35% over conventional CMOS-based SRAM designs. Additionally, the proposed design reduces power consumption by 40% and enhances readwrite speed by 25%. These results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications.

Fully stretchable and skin-mountable ionic-gated organic phototransistors based on elastomeric semiconductor and dielectric

Soft optoelectronics that can be naturally conformable to human skins for noninvasive light-tissue interplays are inspiring for the realization of human–machine interactions, health monitoring, and soft robotics. Advances in material and structural engineering have been made to realize various skin-like electronics/optoelectronics. However, there still exist great challenges such as procedure complexity and high-power dissipation that seriously impede practical applications for these devices. In this work, we demonstrate a fully stretchable and skin-mountable ionic-gated organic phototransistor with an ultra-low power dissipation of 3 nW, high sensitivity up to 103, and a mechanical stretchability of ε = 20%. The phototransistor is composed of an elastomeric ionic gate dielectric layer with ultrahigh capacitance over 1 μF/cm2 and high stretchability up to ε = 50%. Strain-insensitive photodetection of the device is achieved by the nanoconfinement effect existing inside the intrinsically stretchable photoactive semiconductor layer via blending elastic and insulative polymers into an organic bulk heterojunction. Combining with its pronounced electromechanical properties, the stretchable photodetector can be conformable to various body parts for real-time and noninvasive monitoring on different pulse-waves, demonstrating the ability of low-cost and in-home supervision on chronic diseases in daily life.

An ultra-low power dissipation CMOS temperature sensor with an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C

An ultra-low power, high accuracy BJT-based CMOS temperature sensor is presented in this paper. The temperature sensor consists of analog front end (AFE) and hybrid ADC. In AFE design, two dynamic element matching (DEM) control modules are applied to current mirrors and bipolar transistors reduce the mismatch greatly and enhance the sensitivity of the temperature sensor. A hybrid ADC that combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce the power dissipation. The proposed sensor is fabricated in a 0.18 μm CMOS process, occupying an area of 0.14 mm2. The measured results indicate that, the total current is 6.5 μA from a 1.8 V power supply, and achieves an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C.

Speed and Scalability of Ambipolar Deep-Subthreshold TFTs for Ultralow-Power Printed Electronics

This work evaluates the speed and scalability potential of ambipolar deep-subthreshold printed-carbon-nanotube thin-film transistors (CNT-TFTs) for the design of ultra-low-power CMOS-like circuits. Transistor and circuit simulations are developed based on experimental device measurements. Our simulations allow the assessment of this emerging printed electronics technology in terms of speed, energy/power consumption and scalability to digital circuits of progressively higher transistor count including elementary logic gates, ring-oscillators and other representative digital circuits. It is shown that digital circuits based on this technology are compatible with propagation delays ≤ 1 ms per NOT logic gate, while operating at ultra-low supply voltages (0.2 V) and with ultra-low static power dissipation (1 pW). Finally, this study develops Monte Carlo simulations to assess the impact of device parameter variations on the viability of large-scale circuit integration based on ambipolar deep-subthreshold printed-CNT-TFTs.

A Novel Encrypted Computing-in-Memory (eCIM) by Implementing Random Telegraph Noise (RTN) as Keys Based on 55 nm NOR Flash Technology

A novel encrypted Computing-in-Memory (eCIM) architecture is proposed based on 55nm NOR Flash memory technology, wherein the current fluctuations caused by random telegraph noise (RTN) in flash cells are utilized as the intrinsic encryption source. Furthermore, aiming at the low-power consumption with high bit-density, the near-subthreshold region of the flash cell is used for 2-bit/cell operation. It is demonstrated that, in the designed 32-bit floating-point (FP) calculation architecture, ultra-low power dissipation (0.24 pJ/bit) can be achieved with high calculation accuracies after the decryption.

Design and implementation of an N × 32-bit SRAM in QCA using coplanar wire-crossing network

Quantum-dot cellular automata (QCA) is promising nanotechnology that offers an alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale size, ultra-low power dissipation, and Terahertz range operating frequency make QCA more attractive to circuit designers. In QCA designs, wire-crossing techniques are challenging, especially coplanar wire-crossing techniques that endure lower excitation energy at the intersection point. In addition, the latency of the design also increases. In this paper, a new coplanar wire-crossing network (CWN) is reported by addressing the major shortcomings of previous wire-crossing techniques. The proposed CWN is implemented using both the rotating and non-rotating cells. One noticeable upside of this CWN is that it requires only a 0.75 clock cycle delay to complete an arbitrary number of wire-crossing. By utilizing the proposed CWN, a single-layer 16-bit× 32-bit SRAM has been presented with the read/write functionality. To implement the SRAM, we introduce several new structures – a one-bit memory cell, a 4-to-16 decoder, and a 16-to-1 multiplexer that require the minimum number of majority gates, cells, and latency. With these new modules combined with the CWN, the proposed 16 × 32-bit SRAM shows lower latency and area-delay product by up to ~7.5 and ~11 times, respectively, and higher throughputs by more than ten times when compared to existing SRAM designs.

Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme

Quantum-dot cellular automata (QCA) is a promising nanotechnology that offers an alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale size, ultra-low power dissipation, and Terahertz range operating frequency make QCA more attractive to circuit designers. Recently, numerous designs of QCA have been proposed but aren't practically implementable due to random clocks in the design. In QCA designs, there is a need for proper clocking scheme to favour placement and routing and to facilitate QCA nano-computing synthesis. In this paper, a novel design of Binary-Coded Decimal (BCD) adder, based on QCA technology, with a realistic clocking scheme is presented. System simulations of the proposed designs are performed using QCA designer software Ver. 2.0.3 while power dissipation is investigated using the QCA Pro tool. Besides, in terms of power dissipation, the suggested QCA BCD adder dissipates 2.788 × 10−5 mW, whereas CMOS- based design consume 1.34 mW of power.

A Novel Design of Full Adder Cell for VLSI Applications

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high–performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy delay product (EDP) are extracted and compared for proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value 1.377 µW and the NMNFA exhibits highest value 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages proposed adder deliver low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At supply voltage 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported adder MBFA in this paper.

Ultrafast spin wave propagation in thick magnetic insulator films with perpendicular magnetic anisotropy

Magnetostatic forward volume spin-waves (MFVSWs) are magnetic moments propagated perpendicular to the film plane and offer reciprocity configurations, which is suitable for spin-wave logic devices with low power consumption. However, owing to the strong shape anisotropy field, magnetic films are easily magnetized in the film plane. Fabrication of thick magnetic films with low Gilbert damping and large perpendicular magnetization anisotropy was an unsolved problem. The promising materials with low damping and easy to modify properties are ${\mathrm{Y}}_{3}{\mathrm{Fe}}_{5}{\mathrm{O}}_{12}$-based single-crystal films. High quality $({\mathrm{Y}}_{1.26}{\mathrm{Bi}}_{0.18}{\mathrm{Lu}}_{0.96}{\mathrm{Ca}}_{0.6})({\mathrm{Fe}}_{4.4}{\mathrm{Ge}}_{0.6}){\mathrm{O}}_{12}$ micrometer-thick films with strong anisotropy field up to 1862 Oe, narrow out-of-plane ferromagnetic resonance linewidth as low as 2 Oe, and low Gilbert damping approximately $(7.06\ifmmode\pm\else\textpm\fi{}0.15)\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}5}$ grow on the gadolinium gallium garnet substrate successfully. The garnet film shows a MFVSW group velocity of 2.25 km/s, relaxation time 50 ns, and decay length up to $115\phantom{\rule{0.28em}{0ex}}\ensuremath{\mu}\mathrm{m}$, paving the road towards ultralow power dissipation magnonic devices (microwave devices) based on magnetic insulators.

A low-noise on-chip coherent microwave source

The scaleup of quantum computers operating in the microwave domain requires advanced control electronics, and the use of integrated components that operate at the temperature of the quantum devices is potentially beneficial. However, such an approach requires ultra-low power dissipation and high signal quality in order to ensure quantum-coherent operations. Here, we report an on-chip device that is based on a Josephson junction coupled to a spiral resonator and is capable of coherent continuous-wave microwave emission. We show that characteristics of the device accurately follow a theory based on a perturbative treatment of the capacitively shunted Josephson junction as a gain element. The infidelity of typical quantum gate operations due to the phase noise of this cryogenic 25-pW microwave source is less than 0.1% up to 10-ms evolution times, which is below the infidelity caused by dephasing in state-of-the-art superconducting qubits. Together with future cryogenic amplitude and phase modulation techniques, our approach may lead to scalable cryogenic control systems for quantum processors.

Intrinsic Nature of Negative Capacitance in Multidomain Hf0.5Zr0.5O2‐Based Ferroelectric/Dielectric Heterostructures

AbstractHarnessing ferroelectric negative capacitance in Hf0.5Zr0.5O2‐based thin films is promising for applications in nanoscale electronic devices with ultralow power dissipation, due to their ultimate scalability and semiconductor process compatibility. However, so far, it has been unclear if negative capacitance is an intrinsic material property of ferroelectric Hf0.5Zr0.5O2, or if it is an extrinsic effect caused by specific domain configurations and lateral domain wall motion as seen in perovskite ferroelectrics. Here, symmetric and asymmetric Hf0.5Zr0.5O2/Al2O3‐based ferroelectric/dielectric heterostructures are investigated to understand the relationship among depolarization, interfacial charge, domain formation, and negative capacitance. To achieve this, detailed electrical characterization is combined with structural data, analytical modeling, and numerical simulations. The findings suggest that negative capacitance in these ferroelectric/dielectric heterostructures is an intrinsic property of the Hf0.5Zr0.5O2 layer, which has important implications for potential applications. Furthermore, it is experimentally observed that the energy barrier for polarization switching in Hf0.5Zr0.5O2 is largely independent of the domain configuration and layer thickness, which confirms recent predictions by first principles calculations.

Fredkin gate based energy efficient reversible D flip flop design in quantum dot cellular automata

The latest developments in the electronics industry demands for ultra-low power dissipation circuit designing. Reversible logic, an emerging technology for designing digital circuits, is being investigated along with Quantum dot Cellular Automata (QCA) technology for designing high density and ultra-low power circuits in the sub-nano regime. Considering this, in this paper, a new and efficient design of 3x3 reversible Fredkin gate in QCA is proposed which utilizes only 48 cells. It is then used to design a new reversible logic based D Flip Flop. The proposed QCA circuit of reversible D Flip Flop is designed using only 59 cells. From the performance evaluation, it is seen that the proposed reversible logic based D Flip Flop achieves performance improvement of 41% percent in terms of cell count and cell area and 44% in terms of total area from the existing best design in the literature. In addition to this, proposed designs are more energy efficient hence making them more feasible and suitable for implementation in various ultra-low power applications.

Electro-optically tunable laser with ultra-low tuning power dissipation and nanosecond-order wavelength switching for coherent networks

The huge amount of data traffic behind the rapid growth of cloud computing is putting pressure on the operation of mobile fronthauls and data center networks so there is a need to improve their power consumption and latency. We developed an electro-optically tunable laser diode employing a tunable filter that is practically tuned even with small refractive index change of the electro-optic effect. The laser shows a small tuning power dissipation of less than 10 mW for a practical tuning range of over 35 nm with a linewidth of about 350 kHz. We also achieved high-speed optical switching of less than 50 ns for 100 Gb/s coherent signals. In addition to its application in optical communications, the electro-optically tunable laser diode is also beneficial to laser sensing applications because its higher tuning speed increases the time resolution of the sensing system. Furthermore, a narrow linewidth, conventionally difficult to reconcile with high-speed tuning, can also enable a longer sensing distance and/or a higher signal-to-noise ratio when using coherent detection. Our result shows that we can use the electro-optic effect to overcome the limitations of conventional tunable laser diodes and drastically change optical communications and laser sensing systems.

Design and Implementation of a Smart Wireless Fire-Fighting System Based on NB-IoT Technology

The traditional smoke sensing systems have some disadvantages, including high implementation costs, difficulties in perceiving working states, low data accuracy and troubles in uniform and effective management. To address these problems, a new type of smart wireless fire monitoring system based on NB-IoT technology is innovatively designed, which realizes real-time remote monitoring and management. Compared with traditional smoke alarm systems, this system has such advantages as ultra-low power dissipation, lithium-ion battery power, no wiring, remote monitoring, low battery alarm and so forth. With great application prospect, it is worth to develop and rolled out.