Design and implementation of an N × 32-bit SRAM in QCA using coplanar wire-crossing network

Abstract

Quantum-dot cellular automata (QCA) is promising nanotechnology that offers an alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale size, ultra-low power dissipation, and Terahertz range operating frequency make QCA more attractive to circuit designers. In QCA designs, wire-crossing techniques are challenging, especially coplanar wire-crossing techniques that endure lower excitation energy at the intersection point. In addition, the latency of the design also increases. In this paper, a new coplanar wire-crossing network (CWN) is reported by addressing the major shortcomings of previous wire-crossing techniques. The proposed CWN is implemented using both the rotating and non-rotating cells. One noticeable upside of this CWN is that it requires only a 0.75 clock cycle delay to complete an arbitrary number of wire-crossing. By utilizing the proposed CWN, a single-layer 16-bit× 32-bit SRAM has been presented with the read/write functionality. To implement the SRAM, we introduce several new structures – a one-bit memory cell, a 4-to-16 decoder, and a 16-to-1 multiplexer that require the minimum number of majority gates, cells, and latency. With these new modules combined with the CWN, the proposed 16 × 32-bit SRAM shows lower latency and area-delay product by up to ~7.5 and ~11 times, respectively, and higher throughputs by more than ten times when compared to existing SRAM designs.