A shift-register-based QCA memory architecture

Abstract

A quantum-dot cellular automata (QCA) design of an nxm-bit, serial-access, shift-register based memory architecture is presented. The shift-register-based QCA memory architecture maintains data at a stable conformation, which is contrary to traditional data in-motion concept for QCA architectures. The memory architecture is based on an existing dual-phase-synchronized, line-based, one-bit QCA memory cell building block that provides size, density and latency improvements over other known one-bit memory cells through its novel clocking scheme. Read/write latencies up to 2X lower than the existing tile-based architecture with three-phase, line-based memory cells are obtained. Simulations with QCADesigner and HDLQ are performed on a sample 4times8 bit memory architecture implementation to verify functionality.