Ultra-low Power Dissipation Research Articles

Parallelism, Performance, and Energy-Efficiency Tradeoffs for In Situ Sensor Data Processing

The in situ processing of vast amounts of data, available intermittently in networks of sensors, motivates investigation of means for achieving high performance when required, but ultralow-power dissipation when idle. One approach is the use of embedded multiprocessor systems, leading to tradeoffs between parallelism, performance, energy-efficiency, and cost. To evaluate these tradeoffs, and to gain insight for future system designs, this letter presents the design, implementation, and evaluation of a miniature, energy-scalable, 24-processor module, L24, for compute-intensive in situ sensor data processing tasks. The platform provides idle power dissipation over an order of magnitude lower than systems employing a monolithic processor of equivalent performance, while dynamic power dissipation remains competitive. Taking into account both application computation and interprocessor communication demands, it is shown that there may exist an optimum operating voltage that minimizes either time-to-solution, energy usage, or the energy-delay product. This optimum operating point is formulated analytically, calibrated with system measurements and instruction-level microarchitectural simulation, and evaluated for the hardware platform and application presented.

A 228 $\mu$W 750 MHz BPSK Demodulator Based on Injection Locking

An ultra-low-power BPSK demodulator based on injection locked oscillators (ILOs) is introduced in this paper. Two second harmonic ILOs are employed to convert BPSK signals to ASK signals, which are then demodulated by an envelope detector to baseband. For sub-GHz applications, the ILOs are implemented using ring oscillators to allow compact chip area and ultra-low power dissipation. Bit error rate (BER) analysis of this demodulator indicates erroneous polarity flipping of demodulated bits due to phase noise of ILO. The prototype chip is fabricated in a 65 nm CMOS technology that consumes 228 μW of power and occupies 0.014 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Measurement results reveal the demodulation of 750 MHz 5 Mb/S differential BPSK signal with sensitivity of -43 dBm. Theoretical BER analysis has been verified with erroneous flipping observed in the measurement and its probability close to the prediction.

Single-layer MoS2 transistors

Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

An ultra low power, low voltage tailless QFG based differential amplifier with High CMRR, rail to rail operation and enhanced slew rate

This paper proposes a novel tailless ultra low power low voltage high CMRR differential amplifier (D.A.) with rail-to-rail input common mode range (ICMR) based on quasi floating gate (QFG) transistors. For low voltage operation, the tail current source of the conventional D.A. is removed and the resulted lack of CMRR is highly compensated by means of two simple inverters. The required supply voltage is only VGS + VDSsat (with their usual meanings of symbols) which is one VDSsat lower than the required supply voltage for the conventional D.A. Unlike the conventional differential amplifier, slew rate (SR) in the proposed one is not limited by the tail current source and is determined by the amplitude of input signals. The principle of operation, small signal analysis and the formula of the most important parameters of the proposed D.A. are presented. HSPICE simulation results using TSMC 0.18 μm CMOS process parameters and ±0.4 V supply voltage are presented which verify the high performance of the proposed scheme. The simulation results show a rail-to-rail operation and 121 dB CMRR for the proposed tailless differential amplifier. The corner case simulation results are also provided which show a robust performance for the proposed structure. Its unity gain bandwidth product is 72.3 MHz that is 2.31 times larger than that of conventional differential amplifier. Positive and negative SRs are improved by a factor of 7.4 and 3.58 times respectively compared to conventional one. It has also an ultra low power dissipation of 6.89 μW.

Ultralow-Power Complementary Metal-Oxide-Semiconductor Inverters Constructed on Schottky Barrier Modified Nanowire Metal-Oxide-Semiconductor Field-Effect-Transistors

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

An Adaptive Algorithm for Single-Electron Device and Circuit Simulation

Single-electron devices have been widely used in electronics and physics research, and are believed to be one of the potential alternatives to CMOS circuits due to their small size and ultra-low power dissipation. In the recent past, three simulation methods have been used for single-electron device and circuit analysis: the Monte Carlo method, the master equation method, and SPICE using analytic models. Among these, the Monte Carlo method provides excellent accuracy, but is too slow for large-scale circuit simulation. In this work, we propose and develop an adaptive simulation technique based on the Monte Carlo method. This technique significantly improves the time efficiency while maintaining accuracy for single-electron device and circuit simulation. We have shown it is possible to reduce simulation time up to nearly 40 times and maintain an average propagation delay error of 3.4% compared to a nonadaptive Monte Carlo method.

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the ß-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-¿m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios.

A 200 μW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems

The growing interest toward the improvement of patients' quality of life and the use of medical signals in nonmedical applications such as entertainment, sports, and brain-computerinterfaces, requires the implementation of miniaturized and wireless biopotential acquisition systems with ultralow power dissipation. Therefore, this paper presents the implementation of a complete EEG acquisition ASIC tailored towards the needs of such applications, i.e., high-signal quality, low-power dissipation and ease of use. The presented ASIC includes eight readout front-end channels and an 11-bit analog-to-digital converter (ADC). The key to its high performance and low-power dissipation is the new AC coupled chopper stabilized instrumentation amplifier (ACCIA) implementation that uses a coarse-fine servoloop and reaches more than 120 dB CMRR, consumes only 2.3 muA , and achieves a noise-efficiency factor (NEF) of 4.3. Furthermore, the ease of use of the ASIC is realized by incorporating Calibration and Electrode Impedance Measurement Modes to the ASIC. Therefore, the former can be used to check the functionality of the ASIC, as well as, to calibrate the gain matching of the channels, where as the latter can be used to track the quality of the biopotential electrode. The ASIC is implemented in 0.5 mum CMOS process and the total current consumption is 66 muA from 3 V.

1.5 V Sub-mW CMOS Interface Circuit for Capacitive Sensor Applications in Ubiquitous Sensor Networks

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-μm CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 μW of the interfacecircuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

A Statistical Reliability Model for Single-Electron Threshold Logic

As one of the most promising candidates for future digital circuit applications, single-electron tunneling (SET) technology has been used to ensure further feature size reduction and ultralow power dissipation. However, this technology raises very serious concerns about reliable functioning, particularly due to random background charges and tight fabrication tolerances. Accurate evaluation of reliability for SET circuits has thus become a crucial step toward their reliability analysis and improvement. This brief proposes a statistical reliability model for SET logic gates, which takes into account the actual process variations and input probabilities. In particular, we study two typical SET logic gates (two-input nor and nand gates) for gate reliability evaluation. Instead of assuming a constant failure rate for logic gates as in most previous work, we show how logic inputs affect the reliability of the individual gates with discussions on the overall reliability of the system consisting of logic gates. This model can be used in future computer-aided design tools to estimate tunneling events, energy consumption, and reliability of SET-based digital logic circuits.

SEMSIM: Adaptive Multiscale Simulation For Single-Electron Devices

Single-electron devices have drawn much attention in the last two decades. They have been widely used for device research and also show promise as a potential alternative to CMOS circuits due to their ultralow power dissipation. Three techniques have been used for single-electron device modeling in the past, including Monte Carlo (MC), master equation, and SPICE modeling. Among these, MC method provides accuracy, but lacks the time efficiency required for large-scale simulation. In this paper, we introduce an adaptive multiscale approach to single-electron device simulation using MC method as basis, which significantly improves time efficiency while maintaining accuracy. We have shown that it is possible to reduce simulation time up to nearly 40 times and maintain an average error of 3.3%. Going beyond simplistic approximations, we have modeled important secondary effects including cotunneling and Cooper pair tunneling, which are critical for device research.

Development of High-speed and Low-power Microprocessors using Superconductive Circuits

Superconductive single flux quantum (SFQ) circuits, which perform their circuit operations by controlling propagations of flux quanta in connected superconducting rings, can operate at the frequency of several tens GHz with ultra low power dissipation. The SFQ circuit is thought to be an attractive candidate for fundamental elements of future high-end information processing systems. This paper reports the development of SFQ microprocessors for high-end computation systems.

An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RNG), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35μm CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100kbps. It has a typical ultra-low power dissipation of 0.91μW. This novel circuit is a promising unit for low power system and communication applications.

In As ∕ Al Sb high-electron-mobility transistors by molecular-beam epitaxy for low-power applications

In As ∕ Al Sb high-electron-mobility transistor technology has transitioned from research to development stages in recent years. Development efforts at Northrop Grumman Space Technology, in collaboration with the Naval Research Laboratory and the University of California, Los Angeles, have focused on X-band and W-band low-noise amplifier monolithic millimeter-wave integrated circuits fabricated for applications requiring ultralow-power dissipation. The materials for the circuits discussed in this article were grown at Northrop Grumman Space Technology on 3-in.-diameter semi-insulating GaAs substrates by molecular-beam epitaxy. Atomic-force microscopy of the as-grown surface on each wafer showed that the rms roughness for all of the wafers ranged between 0.5 and 3.5nm, and this range of roughness was fully compatible with the fabrication process. The high electron mobility that InAs can provide was achieved reproducibly in these materials. It was maintained almost always above 25000cm2V−1s−1, and in several cases even exceeded 30000cm2V−1s−1. The associated electron sheet concentration ranged between 1.2×1012 and 1.8×1012cm−2. These combined mobilities and sheet concentrations gave corresponding sheet resistances in the range of 170±40Ω∕sq, with nonuniformity below 6% over these 3-in.-diameter wafers. These materials characteristics enabled successful fabrication of several recently published X-band and W-band low-noise amplifier circuits, and figures of merit for the circuits that were made specifically from these materials are referenced in this article.

Bennett clocking of quantum-dot cellular automata and the limits to binary logicscaling

We examine power dissipation in different clocking schemes for molecular quantum-dot cellularautomata (QCA) circuits. ‘Landauer clocking’ involves the adiabatic transition of a molecularcell from the null state to an active state carrying data. Cell layout creates devices whichallow data in cells to interact and thereby perform useful computation. We perform directsolutions of the equation of motion for the system in contact with the thermal environmentand see that Landauer’s Principle applies: one must dissipate an energy of at leastkBT per bit only when the information is erased. The ideas of Bennett can be applied to keepcopies of the bit information by echoing inputs to outputs, thus embedding any logicallyirreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. Apromising alternative which we term ‘Bennett clocking’ requires only altering thetiming of the clocking signals so that bit information is simply held in place bythe clock until a computational block is complete, then erased in the reverseorder of computation. This approach results in ultralow power dissipation withoutadditional circuit complexity. These results offer a concrete example in which toconsider recent claims regarding the fundamental limits of binary logic scaling.

InAs HEMT narrowband amplifier with ultra-low power dissipation

The design, fabrication and performance of a prototype narrowband amplifier using InAs-channel HEMTs are reported. The amplifier, which is realised on an RT/Duroid circuit board with a combination of transmission lines and lumped components, is intended for a long-life battery-powered application. The two-stage amplifier has 20 dB of gain with a bandwidth of 4% in S-band and dissipates a total power of only 365 µW.

SET-based quantiser circuit for digital communications

A single electron transistor (SET)-based quantiser circuit has been developed for the purpose of digital communication. The proposed circuit, which consists of only two SET devices and one load capacitor, offers ultra-low power dissipation, small quantisation noise error and zero granular noise error. The proposed circuit does not require any external sampling signal for sampling the baseband signal, the sampling rate can be controlled by varying the device capacitor.

A new concept for ultra-low power and ultra-high clock rate circuits

Compared with semiconductors, SFQ logic is very fast and dissipates extremely low power. But it does not approach the theoretical power dissipation associated with an SFQ switching event and single gate speed in complex circuits. For large circuits and systems, e.g., petaflops computing, we must reduce on-chip dissipation, achieve faster clocked logic operation, and increase gate density. CMOS logic dissipates the energy required to switch a transistor pair and dissipates no power between switching events. We describe a new SFQ circuit concept that mimics CMOS to achieve ultra-low power dissipation and ultra-high clock rates. This results in physically compact, self-clocked, complementary logic (SCCL), in which clock distribution is frequency-independent. The basic element in this logic family is a simple two-junction comparator. Using TRW's 2 kA/cm/sup 2/ Nb design rules, we simulated basic digital components: shift register, AND, OR, and NOT at 20 GHz. We present the simulated and measured performance.