Abstract
This work evaluates the speed and scalability potential of ambipolar deep-subthreshold printed-carbon-nanotube thin-film transistors (CNT-TFTs) for the design of ultra-low-power CMOS-like circuits. Transistor and circuit simulations are developed based on experimental device measurements. Our simulations allow the assessment of this emerging printed electronics technology in terms of speed, energy/power consumption and scalability to digital circuits of progressively higher transistor count including elementary logic gates, ring-oscillators and other representative digital circuits. It is shown that digital circuits based on this technology are compatible with propagation delays ≤ 1 ms per NOT logic gate, while operating at ultra-low supply voltages (0.2 V) and with ultra-low static power dissipation (1 pW). Finally, this study develops Monte Carlo simulations to assess the impact of device parameter variations on the viability of large-scale circuit integration based on ambipolar deep-subthreshold printed-CNT-TFTs.
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