Ultra-thin SOI MOSFETs Research Articles

Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs

In this paper, the impacts of work function variation (WFV), line-edge roughness (LER), and ferroelectric properties variation on the threshold voltage, subthreshold swing (SS), Ion, and Ioff variations are analyzed comprehensively for negative capacitance ultra-thin body SOI MOSFETs (NCSOI) compared with SOI MOSFETs (SOI). For LER induced threshold voltage variation ( $\sigma $ Vt), NC-SOI MOSFETs exhibit smaller $\sigma $ Vt (= 3.8 mV) than the SOI MOSFETs ( $\sigma $ Vt = 17.6 mV). For analyzing WFV of NC-SOI MOSFETs, two scenarios are considered including (I) same WFV patterns, and (II) different WFV patterns between the external and internal metal gates. Compared with SOI, NC-SOI with scenario (I) exhibits comparable WFV induced $\sigma $ Vt (= 16.2 mV), and NC-SOI with scenario (II) exhibits larger WFV induced $\sigma $ Vt (= 28.5 mV). In scenario (II), different WFV patterns between the internal and external gates result in $\mathrm {V}_{\mathrm {FE}}$ (voltage drop across the ferroelectric layer) variations, which increases the WFV induced $\sigma $ Vt for NC-SOI. LER dominates energy-delay product variations ( $\sigma $ EDP), and NC-SOI MOSFETs show smaller $\sigma $ EDP than SOI MOSFETs. Besides, NC-SOI MOSFETs with thicker ferroelectric layer thickness ( $T_{\mathrm {FE}}$ ), larger coercive electric field ( $E_{C}$ ), and smaller remnant polarization (P0) show smaller LER induced $\sigma $ Vt and $\sigma $ SS. Ferroelectric properties variations show negligible impact on the WFV induced $\sigma $ Vt and $\sigma $ SS.

Analytical subthreshold current modeling of nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical gaussian doping profile

Based on the evanescent-mode analysis, an insightful study of the channel potential is performed for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical Gaussian doping. And a two-dimensional (2D) analytical subthreshold current model is presented. The front and the back channel subthreshold currents are effectively derived using the inversion layer current density model which takes the Gaussian doping into account. The accuracy of the model has been verified by 2D numerical device simulations using Sentaurus Technology Computer-Aided Design (TCAD) from Synopsys. The model provides a deep understanding and can be instrumental for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a non-uniform doping profile operating in the subthreshold regime.

Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD>1.0V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.

Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs

We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations.

Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

Ultrathin-body (UTB) SOI MOSFETs, which possess excellent short-channel effect immunity and high current on-off ratio, are expected to put back the conventional MOSFETs in high performance digital integrated circuits by the end of year 2014 to continue the current scaling trend. In this paper, targeting systems-on-a-chip (SOC) applications, a simulation based extensive study is carried out to evaluate the analog and RF performance of source/drain and gate engineered ultrathin body SOI MOSFETs, as both the digital and analog performance of the device must be excellent for SOC applications. The performance evaluation has been done in terms of device parameters like device capacitances (Cgs and Cgd), drain current (Id), transconductance (gm), transconductance generation efficiency (gm/Id), intrinsic gain (gm/gd), cut-off frequency (fT) and the maximum frequency of oscillation (fmax). The RF figures-of-merit (FoM) i.e., fT and fmax have been determined by using H and Y parameters obtained from high frequency simulation of the structure. The numerical simulation is performed using ATLASTM, a 2-D device simulator from SILVACO Inc.

Mobility Investigation by Geometrical Magnetoresistance in Fully Depleted MOSFETs and FinFETs

The operation of advanced planar MOSFET and FinFET transistors on SOI is investigated under high magnetic field. The geometrical magnetoresistance is observed when the Hall field is suppressed thanks to the device geometry. This method is free from any assumptions (oxide and body thickness, effective channel length, etc.) and delivers the most accurate and indisputable value of carrier mobility. Our measurements show, for the first time, the mobility behavior in FinFETs with double- and triple-gate and in ultrathin SOI MOSFETs. The magnetoresistance reveals the electron mobility in front or back channels as well as the impact of their interaction. A marked difference in mobility value and variation with gate voltage between the front and back channels is highlighted. A mobility discrepancy also appears between planar and FinFET transistors. Nonuniversal mobility curves with multibranch aspect result from the coexistence of several channels. This nonconventional behavior is explained by the variations in effective field and inversion charge centroid. The geometric magnetoresistance effect arises even in the lateral channels of FinFETs, an intriguing aspect that results from the device configuration.

On the gm/ID-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETs

In this paper, we investigate the transconductance-to-current ratio (gm/ID) methods for the threshold voltage extraction using two popular threshold voltage criteria applicable to advanced bulk and SOI MOSFETs, namely: the condition of the maximum of the second derivative of the inversion charge and of the equality of the drift and diffusion drain current components. Using analytical modeling, we derive the first-order electrical parameters matching these two physical conditions and show that in the ideal MOSFET they do not coincide. The first corresponds to the point on the gm/ID versus gate voltage (Vg) curve where d(gm/ID)/dVG exhibits a minimum and where the ratio of gm/ID to its maximum value is equal to 2/3, whereas the second is met at the point where this ratio equals 1/2. The gm/ID methods for the VTH extraction using the above two criteria and their correlation with other methods are discussed. Since our modeling is based on the unified charge control model, its predictions are expected to be valid for both bulk and SOI MOSFETs. Experimental and simulation results for advanced SOI MOSFETs are used to validate modeling derivations and clarify practical applicability and limitations of the gm/ID methods.

Acoustic Phonon and Surface Roughness Spin Relaxation Mechanisms in Strained Ultra-Scaled Silicon Films

We consider the impact of the surface roughness and phonon induced relaxation on transport and spin characteristics in ultra-thin SOI MOSFET devices. We show that the regions in the momentum space, which are responsible for strong spin relaxation, can be efficiently removed by applying uniaxial strain. The spin lifetime in strained films can be improved by orders of magnitude, while the momentum relaxation time determining the electron mobility can only be increased by a factor of two.

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX

Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.

Study of potential high-k dielectric for UTB SOI MOSFETs using analytical modeling of the gate tunneling leakage

In this paper, we use analytical models of the direct tunneling gate leakage current to determine the high-k dielectric suitable for the nanoscale ultra-thin body SOI MOSFET structure with the predicted equivalent oxide thickness (EOT) and the maximum value of gate leakage current according to the requirements of the latest ITRS roadmap for three technological nodes. The most important criteria for selecting alternative dielectrics (maximum gate leakage current, EOT, electron effective mass, dielectric constant k-value, barrier height and SiO2 thickness as an interfacial layer) were taken into account to determine the suitability of the gate oxide materials. In the ideal case without an interfacial layer, HfO2 and Lu2O3 were found to be the best gate oxide materials for the 17, 15 and 14 nm technological node requirements.

Performance of SOI MOSFETs with Ultra-Thin Body and Buried-Oxide

The electrical characteristics in ultra-thin (8 nm) SOI-MOSFETs with 10 nm buried oxide thickness were studied. Threshold voltage was effectively controlled for both of N-channel and P-channel SOI-MOSFETs even in the short devices (45 nm). No degradation of the mobility due to the use of thin buried oxide could be detected. Through appropriate back-gate biasing, the performance of ultra-thin SOI-MOSFETs can be improved dramatically. In P-channel SOI-MOSFETs, the hole mobility measured in volume conduction regime is higher than when only one interface (Si/high-K or Si/SiO2) is activated. This gain makes the hole mobility comparable with the universal mobility law and is promising for performance enhancement in CMOS circuits.

Evaluation of the Interface Trap Density in Ultrathin SOI MOSFETs: Problems and Solutions

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A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.

Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.

Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

The electrical properties of front and back channels in advanced SOI MOSFETs (ultrathin film, short length, metal-gate/high-K stack, thin BOX) are used to reveal the impact of tensile and compressive CESL strain. The benefit of compressive strain is maximized in 100nm long MOSFETs, where the hole mobility can be increased by a factor of two. In shorter devices, the mobility gain fades away due to neutral defects and remote Coulomb scattering. The short-channel scattering and strain mechanisms are identified by low temperature measurements and explained by an original physics-based model.

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction channel in the film from front to back interface, and on the comparison between the two BOX thicknesses. It is found that the back-channel mobility significantly exceeds the front-channel mobility, which is presumably related to strongly different Coulomb scattering at the two interfaces, being in agreement with previously published experimental studies. Furthermore, the back-channel mobility is found to be the same for thick and thin BOX. This strongly suggests that BOX thinning does not degrade the quality of the back interface. The observed effect of much higher back-channel mobility, which is retained for the thin BOX, could find application for the additional improvement of the device performance, when adjusting the threshold voltage via back-gate bias. Adequate mobility interpretation is then required as a varying combination of front and back-channel mobilities.

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage (Vthf) and subthreshold slope (S), for sub-32nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145nm (UTB) or thin 11.5nm (UTB2). This study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1μm down to 25nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact on the electrical parameters Vthf and S. Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling.

Quantum transport in an ultra-thin SOI MOSFET: Influence of the channel thickness on the I–V characteristics

Quantum mechanical features of the electron transport in a SOI MOSFET are described within the Wigner function formalism which explicitly deals with electron scattering due to ionized impurities, acoustic phonons and surface roughness at the Si/SiO 2 interface. The calculated device characteristics are obtained as a function of the thickness of the semiconductor layer. An analysis of the I–V characteristics of the MOSFET shows a substantial reduction of the short-channel effect with a decrease in the channel thickness of the device.