Ultra-thin SOI MOSFETs Research Articles

Investigation of SOI MOSFETs with ultimate thickness

Ultra-thin SOI MOSFETs with 1–5nm thick SOI film, are experimentally and theoretically investigated. Single- and double-gate configurations are compared; the double-gate MOSFET exhibits a substantial increase in transconductance, presumably resulting from volume inversion. Most of the experimental data can be explained by combining classical models with self-consistent quantum calculations. The characteristics are well-behaved and reveal unique “ultra-thin” film properties: enhanced interface coupling and body-substrate coupling, degraded mobility, increased threshold voltage.

Review of low-voltage CMOS LSI technology as a standard in the 21st century

Recently proposed low-voltage circuit techniques are reviewed and important topics in the process and device fields to make practical low-voltage circuits are discussed in preparation for the coming low-voltage era. A common concept of a low-voltage circuit is defined: that is using low-threshold-voltage ( V t) MOSFETs for high-speed and reducing subthreshold leakage current by using an effective high- V t MOSFET. Some circuits, MTCMOS and VTCMOS, and very-low-voltage circuits using an ultra-thin SOI MOSFET are described. The extreme importance of voltage control for low-voltage LSI operation is emphasized and approaches from the process and the system side (power management) are described. The low- V t device structure for small sub-threshold swing and for preventing short-channel effects due to the channel engineering are discussed. The necessity of a new screening method, especially for low- V t LSIs, and some interesting features in temperature dependence are also discussed.

Floating Body and Hot Carrier Effects in Ultra-Thin Film SOI MOSFETs

Floating body and hot carrier effects are thoroughly investigated in deep submicron N- and P- channel ultra-thin film SOI MOSFETs for a wide temperature range. A strong reduction of the parasitic bipolar transistor is obtained with decreasing the temperature (at 77K) and with a grounded substrate. However, the action of the PBT is not completely suppressed even at 77K with a body terminal. Substantial deviations from the traditional bell-shaped curves are found for the substrate current in N- and P- channel SOI devices and are attributed to the PBT carrier transport. The influence of these special SOI mechanisms on gate current is also underlined. Finally, original variations of hot carrier effects as a function of the temperature are shown and explained by the aforementioned SOI electrical properties and the differences between inversion and accumulation-mode devices.

Reliability of ultra-thin SOI MOSFET's

The hot-carrier-injected oxide regions in the front and back interfaces are systematically clarified for fully depleted surface-channel nMOSFET's and surface-channel and buried-channel pMOSFET's on SOI, which is essential to understand hot carrier reliability. The influence of these injected carriers on the front-channel properties is investigated. A new hot-carrier degradation mode peculiar to MOSFET's on SOI is described. This mode is caused by suppression of parasitic bipolar action due to hot-carrier-induced front interface traps. The reliability lifetime of nMOS and pMOSFET's is also discussed, considering the new degradation mode.

Elimination of parasitic bipolar-induced breakdown effects in ultra-thin SOI MOSFETs using narrow-bandgap-source (NBS) structure

In this paper, we introduce the Si-SiGe narrow bandgap-source (NBS) SOI device structure in order to improve the low drain-to-source breakdown voltage (V/sub BD/) in ultra-thin SOI devices. Reducing the potential barrier of valence band between source and body by applying the SiGe layer at the source region, we can improve the drain-to-source breakdown voltage by suppressing the hole accumulation in the body. As confirmed by 2D simulation results, NBS-SOI devices provide excellent performance compared to conventional SOI devices. >

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n/sup -/ region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n/sup -/ concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n/sup -/ region, which forms the current path, was relaxed effectively at an optimum n/sup -/ doping condition. >

High performance ultrathin SOI MOSFET's obtained by localized oxidation

In this paper, we present a new and simple method to process ultrathin fully depleted SOI MOSFET's. Series resistance problems in the full-wafer thinning method are presented and compared with our locally thinned process. Device design of the method is also discussed in terms of current level. The comparison of different process architectures allows us to define the best design rules for these transistors. To validate the method, experimental characteristics of locally thinned accumulation-mode MOSFET's are presented. >

Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices

The electrical characteristics of modern VLSI and ULSI device structures may be significantly altered by self-heating effects. The device modeling of such structures demands the simultaneous simulation of both the electrical and the thermal device behavior and their mutual interaction. Although, at present, a large number of multi-dimensional device simulators are available, most of them are based on physical models which do not properly allow for heat transport and other nonisothermal effects. This paper, demonstrates that the numerical process/device simulator TRENDY provides a solid base for nonisothermal device simulation, as a physically rigorous device model of carrier and heat transport has been incorporated in the TRENDY program. With respect to the boundary conditions, it is shown that inclusion of an artificial boundary material relaxes some fundamental physical inconsistencies resulting from the assumption of ideal ohmic contact boundaries. The program TRENDY has been used for studying several nonisothermal problems in microelectronics. As an example, the authors consider an ultra-thin SOI MOSFET showing that the negative slopes in the V/sub ds//spl minus/I/sub ds/ characteristics are caused by the temperature-dependence of the electron saturation velocity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFET's with low source/drain series resistance. Thin-film fully depleted SOI MOSFET's with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance. >

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics. >