Ultra-thin-body Silicon-on-insulator Research Articles

Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifiers

In the nanoscale domain, the MOSFETs are prone to various physical effects due to their shorter channel region known as short-channel effects (SCE). The researchers have proposed an advanced structure of MOSFET known as the ultrathinbody silicon-on-insulator (UTBSOI) to overcome the limitations of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET having superior controllability of gates over the shorter channel region. Nowadays, the UTBSOI MOSFETs can be adopted in the circuit simulators through the use of a device model named BSIM-IMG. The BSIM-IMG has made it possible for the circuit designers to simulate any UTBSOI based analog blocks like operational amplifiers (opamp). The performance parameters of an opamp are very much sensitive to any perturbation in size (W/L) of the constituent MOSFETs, that may cause a drastic change in the output. In this paper, the sensitivity analysis procedure has been proposed for the CMOS and UTBSOI based two-stage opamps as the function of perturbation in W/L. In addition to this, an algorithm has also been presented to do the same. From the simulation results, it is observed that the sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is larger than that of CMOS based opamp (CMOS-opamp).

Epitaxial Oxides on Glass: A Platform for Integrated Oxide Devices

The fabrication of epitaxial, ultra-thin SrTiO3 (STO) on thick SiO2 without the need for complicated wafer-bonding processes has been demonstrated. The resulting transition metal oxide (TMO)-on-glass layer stack is analogous to traditional silicon-on-insulator (SOI) wafers, where the crystalline device silicon layer of SOI has been replaced by a crystalline functional TMO layer. Fabrication starts with ultra-thin body SOI on which crystalline STO is grown epitaxially by molecular beam epitaxy. The device silicon layer is subsequently fully oxidized by ex situ high-temperature dry O2 annealing, as confirmed by X-ray photoelectron spectroscopy, X-ray reflectivity, and high-resolution electron microscopy. STO maintains its epitaxial registry to the carrier silicon substrate after annealing and no evidence for degradation of the STO crystalline quality as a result of the TMO-on-glass fabrication process is observed. The ease of fabricating the TMO-on-glass platform without the need for wafer bonding will enab...

Effect of Microwave Annealing on the Interface Properties Between the Top Silicon and Buried Oxide Layers in Silicon-on-Insulator MOSFETs

In this paper, a post-annealing process that uses microwaves to remove the back-interface thermal damage at the interface between the top silicon layer and the buried oxide layer of a silicon-on-insulator (SOI) device caused during rapid thermal annealing (RTA) was studied. RTA, which is widely used in highly integrated short-channel silicon device manufacturing processes, deteriorates the electrical characteristics of SOI pseudo metal-oxide-semiconductor field-effect transistors (MOSFET) by affecting the interfacial properties between the top silicon and buried oxide layers. In order to replenish these interfacial properties, microwave annealing (MWA) was performed on the device under various conditions. Because MWA utilizes the direct energy transfer (DET) method, the RTA-induced thermal damage on the back interface was effectively removed despite a short processing time. The improvement was comparable to that of conventional thermal annealing at a higher temperature for a long period of time. Therefore, MWA is expected to be a very effective post-RTA heat-treatment technology for fabricating ultrathin-body SOI MOSFETs because of its low thermal budget.

Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

Implementation Topology of Full Adder Cells

Abstract Design of different complementary metal-oxide-semiconductor (CMOS) topologies of 1-bit full adder (FA) cell in terms of power, delay, power-delay-product (PDP) and energy-delay-product (EDP) have been analyzed for the application of the intelligent systems. The FA cells have been implemented with respect to the different CMOS topologies such as complementary-CMOS (C-CMOS), complementary pass-transistor logic (CPL), CMOS transmission gates (TGA), and CMOS transmission function (TFA) and simulated at 180 nm technology. The work has been extended to the comparison of FA cell implementation using the increasingly demanding ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Based on the simulation results, the application of UTBSOI in the FA cell has resulted in 26.7%, 24.3%, 44.6% and 44.7% improvements over that of best design architecture reported in this literature in terms of power, delay, PDP, and EDP, respectively.

Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors

Abstract In the modern electronic devices, compressor circuits are used to speed up the partial product addition (PPA) stage in the multipliers. This paper presents an architecture of multi-column 5,5:4 compressor whose new transistor level implementation has been carried out through the ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Such compressor has been simulated in Cadence-spectre, and the performance parameters like power consumption and delay has been calculated at the rising and falling edge transition of input pulses. Advantage of the UTBSOI-compressor is further clarified from its comparison with the CMOS based design (CMOS-compressor). Simulation results reveal that the PDP exhibited by the UTBSOI-compressor is reduced by 79.89% than that of CMOS counterparts. Furthermore, to showcase the advantage of such compressor, it has been applied in the multiplier for PPA which offers ≈11.5% improvement in terms of power-delay-product (PDP) in the Virtex 6 platform.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling

The charge coupling between the front and back gates is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOSFET. It is traditionally described by the classical Lim and Fossum model (Lim and Fossum, 1983). However, in the case of lightly-doped ultra-thin-body (UTB) SOI MOSFETs with ultra-thin gate dielectrics, significant deviations from this model have been observed and analyzed over the years. In this paper, we present a thorough review of special features of gate coupling in such devices, combining a large set of results from one-dimensional numerical simulations in classical and quantum–mechanical modes, experimental data and analytical modeling. We show that UTB SOI MOSFETs with ultra-thin gate dielectrics feature stronger modulation of the threshold voltage at the conduction side with opposite gate bias and much wider range of gate voltages for interface coupling than predicted by the Lim and Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects is presented. The model enables an easy assessment of the quantization-induced threshold voltage increase in a long-channel SOI MOSFET versus opposite gate bias and the electric field in the silicon film associated with gate decoupling.

An Improved Model of Self-Heating Effects for Ultrathin Body SOI nMOSFETs Based on Phonon Scattering Analysis

Self-heating effects of ultrathin body silicon-on-insulator (SOI) structure are studied by introducing the phonon scattering mechanisms. An improved model of self-heating effects is present considering the heat generation and the thermal diffusion mechanisms. The thermal conductivity parameters are extracted using transient plane source method from the experiment data. The temperature distributions caused by self-heating effects in the silicon layer of SOI nMOSFETs are verified by the numerical Sentaurus TCAD simulation data. The results show that with the thickness of the silicon layer between the gate and the buried oxide decreasing down to sub-20 nm, the phonon scattering rate of free and bound electrons, and the boundary reflection should be taken into consideration in the modeling of self-heating effects.

Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi Approach

Using a novel Voronoi method that can provide a more realistic representation of metal-gate granularity, we investigate and compare the impact of work-function variation (WFV) on FinFET and ultrathin body (UTB) silicon-on-insulator (SOI) devices. Our study indicates that, for a given electrostatic integrity and total effective gate area, the FinFET device exhibits better immunity to WFV than its UTB SOI counterpart. We further show that, unlike other sources of random variation, the WFV cannot be suppressed by equivalent oxide thickness scaling.

Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ∼40% and ∼20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes.

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

This paper presents a study of the effect of the gate-voltage-dependent mobility on the threshold voltage extraction in long-channel MOSFETs by the transconductance change method and recently proposed transconductance-to-current ratio change method, using analytical modeling and experimental data obtained on advanced silicon-on-insulator (SOI) FinFETs and ultrathin-body SOI MOSFETs with ultrathin high- gate dielectrics. It is shown that, at vanishingly small drain voltage and constant mobility, both methods yield the same values, coinciding with the position of the maximum of the second derivative of the inversion carrier density in respect to the gate voltage. However, such is not the case anymore when considering gate-voltage dependence of mobility around threshold. Analytical expressions for the errors in the values obtained by both methods due to mobility variation around threshold are obtained. Based on analytical modeling and experimental data, it is demonstrated that, for the same mobility variation, the resulting error on the extraction caused by the gate-voltage-dependent mobility is much smaller for the transconductance-to-current ratio change method than for the transconductance change method.

Defect Characterization in SiGe/SOI Epitaxial Semiconductors by Positron Annihilation

The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors has been demonstrated in thin multilayer structures of SiGe (50 nm) grown on UTB (ultra-thin body) SOI (silicon-on-insulator). A slow positron beam was used to probe the defect profile. The SiO2/Si interface in the UTB-SOI was well characterized, and a good estimation of its depth has been obtained. The chemical analysis indicates that the interface does not contain defects, but only strongly localized charged centers. In order to promote the relaxation, the samples have been submitted to a post-growth annealing treatment in vacuum. After this treatment, it was possible to observe the modifications of the defect structure of the relaxed film. Chemical analysis of the SiGe layers suggests a prevalent trapping site surrounded by germanium atoms, presumably Si vacancies associated with misfit dislocations and threading dislocations in the SiGe films.

Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI MOSFETs

Abstract The subthreshold conduction regime in short-channel recessed source/drain (ReS/D) ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs is studied. A physics-based model for the subthreshold slope of ReS/D UTB SOI MOSFETs is developed, based on an analytical solution of 2-D Poisson’s equation for the front-gate and back-gate potential distributions. In order to verify the accuracy of the model, the calculated subthreshold slope values are compared with the results obtained by Medici 2-D numerical device simulator over a wide range of different device structures, and very good agreement is obtained down to channel lengths of sub-30 nm. The model is given in explicit form without any fitting parameters and requires no iterative calculation, thus making it ideally suitable for fast prediction and evaluation of device design criteria for optimal scaling of the ReS/D UTB SOI MOSFETs.

Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure

Optimization of the series resistance of silicide contact structure in ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFET with elevated source/drain (S/D) is examined through theoretical analysis and 2-dimensional simulation. It is found that the optimum silicide/Si interface position, which exhibits lowest parasitic series resistance, can be located at inside of SOI layer under the surface as the effective contact length is scaled down further below 100 nm regime. The closed-form analytical expressions derived from modified transmission line model principle provide a guideline for optimum design of silicide thickness and contact parameters in self-aligned silicide technology.

Double step buried oxide (DSBO) SOI-MOSFET: A proposed structure for improving self-heating effects

For the first time, a novel structure named as double step buried oxide silicon-on-insulator-MOSFET (DSBO-SOI) is proposed, which can combine the advantages of both SOI structure and bulk structure. Design consideration for a 30 nm channel length SOI-MOSFET employing double step buried oxide (DSBO) is presented. The electrical characteristics and temperature distribution are analyzed and compared with ultra-thin body silicon-on-insulator (UTB-SOI) MOSFET. The DSBO devices are shown to have better leakage and sub-threshold characteristics. Furthermore, the channel temperature is reduced during high-temperature operation and drain current increase suggesting that DSBO can mitigate the self-heating penalty effectively. Our results suggest that DSBO is an alternative to silicon dioxide as the buried dielectric in SOI, and expands the application of SOI to high temperature.

Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs

Front-gate and back-gate potential distributions and threshold voltage of recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are modeled. The analytical expressions of the front-gate and the back-gate potential distributions are derived by assuming a parabolic potential variation perpendicular to channel and by solving 2D Poisson’s equation. Based on strong inversion criterion applied to the surface potential minimum value, threshold voltage model of the short channel ReS/D UTB SOI MOSFETs is derived. The model is verified by comparison with 2D numerical device simulator over a wide range of different material and geometrical parameters and very good agreement is obtained.

Performance Prediction of Graphene-Channel Field-Effect Transistors

We compare the threshold voltage and subthreshold-slope characteristics as measures of short-channel effects (SCEs) for graphene-channel field-effect transistors (GFETs) with wide bilayer armchair-graphene film with those for ultrathin-body silicon-on-insulator (UTB-SOI) MOSFETs using a drift-diffusion-based device simulator. The intrinsic delay times for GFETs are also compared with those for UTB-SOI MOSFETs.

Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs

We present an analytic, explicit and continuous charge model for a long-channel UTB (ultra-thin body) SOI (silicon-on-insulator) MOSFET, from which analytical expressions of the total capacitances are obtained. Our model is valid from below to well above threshold, without suffering from discontinuities between the regimes. It is based on a unified charge control model derived from Poisson’s equation. The drain-current, charge and capacitances expressions result in continuous explicit functions of the applied bias. The calculated capacitance characteristics are validated by 2D numerical simulations showing a very good agreement for different silicon film thicknesses.