Ultra-thin Body And Box Research Articles

TLP/VFTLP investigation on eNVM 1T1R PCM in FD-SOI UTBB CMOS technology at room temperature

Intrinsic robustness against electrostatic discharge (ESD) like HBM or CDM is a major concern for the reliability and functionality in advanced CMOS FD-SOI technology and especially for non-volatile memory (eNVM). And it is well known that device characterizations are a first step of an ESD investigation. Thus, this R&D study the experimental results from 100 ns to 1 ns transmission line pulse (TLP-VFTLP) on 1T1R phase change memory (PCM) at 300 mm wafer level and at room temperature are reported here. Two types of devices are fabricated and characterized in the standard fully depleted (FD) silicon-on-insulator (SOI) with ultra-thin body and BOX (UTBB). These devices have no additional technological step and are embedded in the final memory cell topology with its selector NMOS transistor. The idea is to evaluate the behaviour of the 1T1R device under transmission line pulse stress with different stress durations. TLP/VFTLP I-V curves are reported and discussed along with post-DC responses to determine the magnitude of the phase change generated by the ESD pulse. These characterizations are important for automotive, micro-controllers, neuromorphic computing and spatial applications depending on their dedicated mission profiles at room or cryogenic temperature.

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain.

A Capacitance Model for Front- and Back-Gate Threshold Voltage Computation of Ultra-Thin-Body and BOX Double-Insulating Silicon-on-Diamond MOSFET

In this paper, a capacitance model for near threshold voltage computation of Ultra-Thin-Body and BOX (UTBB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is proposed. The transistor has a second insulating layer on top of the first insulating layer of a conventional SOD MOSFET which partially covers the diamond layer. The device’s simulation results of the front- and back-gate threshold voltages and the computed model’s threshold voltages - in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses - are compared. In addition, length of the source/drain overlap with the second insulating layer is varied and the device simulation results are compared with those of the model findings. Results of the aforesaid comparison are found to be promising; more than 20 mV change in front-gate threshold voltage is observed at the range of 5 nm to 43 nm. Moreover, the model is found to be applicable in computations of front- and back-gate threshold voltage of 22 nm DI UTBB SOD MOSFET for low drain voltages. Finally, the model’s physical findings present insight on the device’s parameters that directly influence the threshold voltage

An Electron Waveguide Model for FDSOI Transistors

We extend our previous semi-empirical model for quantum transport in a conventional nano-MOSFET to FDSOI transistors. In ultra-thin-body and -BOX (UTBB) FDSOI transistors, the electron channel can be treated as an electron waveguide. In the abrupt transition approximation, it is possible to derive an analytical approximation for the potential seen by the charge carriers. With these approximations we calculate the threshold voltage and the transfer characteristics, finding remarkably good agreement with experiments in the OFF-state given the relative simplicity of our model. In the ON-state, our theory fails because Coulomb interaction between the free charge carriers and the device heating is neglected in our approach.

Intrinsic ESD robustness on new high voltage N/PMOS devices in 28 nm FDSOI UTBB CMOS technology through TLP/VFTLP characterizations

The robustness of intrinsic electrostatic discharge (ESD) is a major topic for the fabrication of advanced CMOS technology and in particular for high voltage (HV) N/PMOS transistors. In this study, it is reported the way to fabricate a HV MOS in standard 28 nm fully depleted (FD) silicon on insulator (SOI) with ultra-thin body and BOX (UTBB). This new device is without extra technology steps and without extra cost. This solution is based on layout design approaches with different flavours of back gate. Afterwards, DC characterizations on booth N & P MOS transistors are presented and discussed. The next step is to investigate the intrinsic ESD robustness on these devices through transmission line pulse (TLP) characterization at room temperature. It appears an interesting intrinsic robustness for this kind of devices. These preliminary results will be useful to use these devices in HV applications with a dedicated ESD protection and this solution lead to be more competitive on FDSOI technology nodes.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

Influence of Supply Voltage and Body Biasing on Single-Event Upsets and Single-Event Transients in UTBB FD-SOI

In this article, we present the effects of voltage scaling and forward body biasing (FBB) on single-event effect sensitivity of a 28-nm ultra-thin body and box (UTBB) fully depleted silicon on insulator (FD-SOI) technology. Heavy-ion irradiation was performed for single-event upset (SEU) and single-event transient (SET) sensitivity assessment on characterization test chips under three supply voltages, with and without back-gate voltage application. Measurements show a steady SEU sensitivity for any supply voltage across the two FBB configurations, whereas SET sensitivity is diminished under FBB. SPICE and TCAD mixed-mode simulations were run to assess the contribution of electrical factors as well as charge extraction mechanisms. While drive strength is increased under FBB, the bipolar amplification plays an important role in sensitivity at low linear energy transfers (LETs).

Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor ( $\gamma $ ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that $\gamma $ variability follows Pelgrom’s rule.

Investigation of built-in bipolar junction transistor in FD-SOI BIMOS

The built-in bipolar junction transistor (BJT) of a BIMOS fabricated in 28 nm ultra-thin body and BOX (UTBB) fully-depleted silicon-on-insulator (FD-SOI) high-k metal gate technology is investigated in common-emitter mode and in built-in metal-oxide-semi-conductor field effect transistor (MOSFET) off-state. In the weak VBE regime, field-effects dominate, generating a negative base current and making the current gain β0 meaningless. For VBE high enough, the BJT works normally but with a very low gain below 1.

UTBB-Based Single Transistor Image Sensor of Submicron Pixel Using Back Gate Modulation

Image sensor has developed for decades. Now, submicron photo sensor device with high performance is required. In this work, a UTBB (ultra-thin body and box) based single transistor image sensor has been investigated. The light collection and signal readout are accomplished by a single transistor, so the pixel of the UTBB image sensor can shrink down to the submicron. The main parameters impacting the performance of the UTBB image sensor such as back voltage, the thickness of the BOX, well doping concentration and well depth are investigated. Besides, the UTBB image sensor can achieve multi-resolution to adapt to different requirements. The performance of the UTBB image sensor is evaluated by TCAD simulations.

On the Low-Frequency Noise Characterization of Z2-FET Devices

This paper addresses the low-frequency noise characterization of Z 2 -FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed.

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8–11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4–5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.

Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Measuring single-event transient (SET) pulse widths is critical for developing proper mitigation schemes to single-event effects (SEE), especially for advanced technologies. This paper presents a test chip design implementing advanced techniques for measuring SETs implemented in a 28 nm Ultra-Thin Body and Box (UTBB) FDSOI technology. Experimental results of heavy ion and Co-60 irradiation experiments are presented. The heavy ion experiments confirm that this technology has very low SEE sensitivity. Laser test results show that pulse distortion (broadening) plays a key role when evaluating the effect of SETs. Total Ionizing Dose (TID) effects were also evaluated by measuring the Ring Oscillator (RO) frequencies and static current during heavy ion and Co-60 irradiation. Experimental results showed that the RO frequencies degraded up to 10% (heavy ion), and 40% (Co-60) after 1000 krad(Si) irradiation, but the logic in the chip functioned without error.

Low Power FDSOI Technology and Devices for RF Applications

: We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TBOX) of 20nm and is similar to that described previously[1]. The use of the backgate gate is shown to dynamically change the operating range and expand the dynamic range for RF. Competitive f T s are reported for nFETs. The thin body architecture demonstrates high self gain. The technology is shown to be well optimized for applications like IoT where low power and RF performance are a premium. UTBB FDSOI technology offers a superior technology for IoT because of the low power performance of the technology and RF performance. A TEM micrograph of the nFET silicon channel and pFET SiGe channel is sown in Figure 1. The high K metal Gate, thin channel silicon and SiGe channel, and raised source drains architecture can be seen clearly seen in the tem Micrographs. The FDSOI transistor has a back gate electrode which provides a unique capability to shift the threshold voltage and operating point of the transistor. This capability is shown in Fig. 2 and Fig. 3 which is a linear plot of Id versus Vgs for Vbg = -2, 0, and 2 Volt bias for the nFET and pFET respectively. The Drain current is well behaved and is shown to shift as the back bias changes the threshold voltage. The digital low power performance of the technology is derived by the absence of drain to source leakage path and a steep subthreshold slope. The thin silicon channel and SiGe channel of 7nm prevents a leakage path and provides a fully depleted channel with superior electrostatics The technology Idsat current reaches 900μA/μm and 670μA/μm for NFET and PFET respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.8V. The Log Id vs Vgs plots for the nFET and pFET are shown in Fig. 4 at a gate length of 20nm. The subthreshold slope of 85 mV/decade demonstrates the steep subthreshold that enables a low threshold voltage to be maintained with low leakage. The output characteristic for nFET Lg=30nm is shown in Fig. 5. The flat shape of the curve also indicates both nFET has low gDs. Out conductance curves (not shown here) show no roll-off at high Vd indicating little if any self heating. In this FDSOI technology the nFET tansconductance reaches gM ~ 1.8mS/um at Lg=20nm and the pFET transconductance reaches gMsat ~ 1.2.mS/um. The gMsat operating point may be adjusted with back gate bias as is shown in Fig. 6 for the nFET with a back gate bias with -2, 0, and 2 volts. The ratio of gMsat/gDS is the self gain wich is enhanced in fully depleted FDSOI technology. The self gain for the nFET is shown in Figure 7 with a back gate bias with -2, 0, and 2 volts. RF Performance is extremely important for IoT and other applications. The RF simulated RF performance of the nFET achieves a peak f T of over 300 GHz as is shown in Figure 8 which plots f T vs Vgs for Vbg = -2, 0, and 2 Volts. Note how the operating point can be moved around just as in the gMsat figure by applying the appropriate back gate bias. This expanded dynamic range is also true for the pFET operation. These are the first FDSOI RF characterization results published on a 20nm Lgate HiKMG process.

Low Power FDSOI Technology and Devices for RF Applications

We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TBOX) of 20nm and is similar to that described previously[1]. The use of the backgate gate is shown to dynamically change the operating range and expand the dynamic range for RF. Competitive fTs are reported for nFETs. The thin body architecture demonstrates high self gain. The technology is shown to be well optimized for applications like IoT where low power and RF performance are a premium.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 V $_{\rm PP}$ with a measured input sensitivity of 10 mV $_{\rm PP}$ at 40 Gb/s, and requires at least 40mV $_{\rm PP}$ input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the > 4V $_{\rm PP}$ swing series-stacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-to-Rx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.

Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

This work provides a detailed study of 28nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are determined. It is shown that fT of ∼280GHz and fmax of ∼250GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S-parameters.

Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300mV of supply voltage, a 4×4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOS⧹ DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.