Abstract
This paper addresses the low-frequency noise characterization of Z 2 -FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.