Ultra-low Specific On-resistance Research Articles

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

A New SiC Quasi MOSFET for Ultra-Low Specific On-Resistance and Improved Reliability

A New SiC Quasi MOSFET for Ultra-Low Specific On-Resistance and Improved Reliability

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (R on,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases R on,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the R on,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 /R on.sp) increases remarkably from 2.15 MW·cm−2 to 18.13 MW·cm−2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

Experiments of Sub-Micron Superjunction Devices With Ultra-Low Specific On-Resistance

A sub-micron superjunction (SM SJ) device with ultra-low specific on-resistance <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is proposed and experimentally realized in this letter. The new device features a surface SM SJ with a mean ion implantation depth of 190 nm and a bulk curvature effect suppressing layer (CSL) with a junction depth of 3.7 μm. The highly doped SM SJ acts as a ultra-low resistance current path to reduce the specific on-resistance <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> meanwhile the CSL shields the possible curvature effect for high breakdown voltage <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> . Experiments of the SM SJ device demonstrated a significantly increased total N-type doping dose up to 9.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> that is almost 10 times of the conventional RESURF dose. A measured low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 27.8 mΩ∙cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was observed under a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 622.6 V, realizing a high figure of merit <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FOM</i> = <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 13.94 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a reduction of 62.2% when compared with the theoretical limit of the triple RESURF technology under the same <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> .

A FIN-LDMOS with Bulk Electron Accumulation Effect.

A thin Silicon-On-Insulator (SOI) LDMOS with ultralow Specific On-Resistance (Ron,sp) is proposed, and the physical mechanism is investigated by Sentaurus. It features a FIN gate and an extended superjunction trench gate to obtain a Bulk Electron Accumulation (BEA) effect. The BEA consists of two p-regions and two integrated back-to-back diodes, then the gate potential VGS is extended through the whole p-region. Additionally, the gate oxide Woxide is inserted between the extended superjunction trench gate and N-drift. In the on-state, the 3D electron channel is produced at the P-well by the FIN gate, and the high-density electron accumulation layer formed in the drift region surface provides an extremely low-resistance current path, which dramatically decreases the Ron,sp and eases the dependence of Ron,sp on the drift doping concentration (Ndrift). In the off-state, the two p-regions and N-drift deplete from each other through the gate oxide Woxide like the conventional SJ. Meanwhile, the Extended Drain (ED) increases the interface charge and reduces the Ron,sp. The 3D simulation results show that the BV and Ron,sp are 314 V and 1.84 mΩ∙cm-2, respectively. Consequently, the FOM is high, reaching up to 53.49 MW/cm2, which breaks through the silicon limit of the RESURF.

Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance

A novel multi-dimensional accumulation gate (MDAG) lateral double-diffused MOS (LDMOS) with ultra-low specific on-resistance (Ron,sp) is proposed and investigated by simulation. The MDAG LDMOS is composed of the MDAG, the trench source, and the N-Buffer. In the on-state, the bulk electron channels are formed in the P-well and the multi-dimensional electron layers are formed in the drift region. Meanwhile, the trench source shortens the current path length. Thus, the Ron,sp is greatly reduced. In the off-state, the N-Buffer is used to form a PN junction with the P-Substrate to obtain the ideal reverse characteristics of the accumulation model LDMOS, and thus the high breakdown voltage (BV) is achieved. The simulation results show that the proposed MDAG LDMOS has a Ron,sp of 0.33 mΩ cm2 and a BV of 181.4 V. The figure of merit (FOM) is as high as 99.7 MW/cm2. Hence, the tradeoff between Ron,sp and BV is greatly improved, and the silicon limit of RESURF is broken.

A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance

A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode (Hk-SJ-SBD MOSFET) is proposed, and has been compared with the SiC high-k MOSFET (Hk MOSFET), SiC superjuction MOSFET (SJ MOSFET) and the conventional SiC MOSFET in this article. In the proposed SiC Hk-SJ-SBD MOSFET, under the combined action of the p-type region and the Hk dielectric layer in the drift region, the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance (R on,sp). The integrated Schottky barrier diode (SBD) also greatly improves the reverse recovery performance of the device. TCAD simulation results indicate that the R on,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm2 with a 2240 V breakdown voltage (BV), which is more than 72.4%, 23%, 5.6% lower than that of the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET with the 1950, 2220, and 2220 V BV, respectively. The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC, which are greatly reduced by more than 74% and 94% in comparison with those of all the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET, due to the integrated SBD in the proposed MOSFET. And the trade-off relationship between the R on,sp and the BV is also significantly improved compared with that of the conventional MOSFET, Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature, respectively. In addition, compared with conventional SJ SiC MOSFET, the proposed SiC MOSFET has better immunity to charge imbalance, which may bring great application prospects.

An ultralow specific on-resistance bidirectional trench power MOSFET with RESURF stepped oxide

This paper presents an ultralow specific on-resistance (Ron,sp) bidirectional trench power metal-oxide-semiconductor field effect transistor (MOSFET) with RESURF stepped oxide (RSO) for lithium-ion (Li-ion) battery protection circuit application. Compared with the conventional dual die bidirectional switches, the proposed single die structure almost halves the total die area with the same cell pitch. Moreover, the drift region under reverse blocking condition is a 2-D depletion and due to the RSO-assisted depletion effect, the concentration of the drift region under reverse blocking condition can be approximately increased by one order, thus a smaller on-state resistance is obtained. Besides, the parasitic transistor is well suppressed due to the cathode short structure for forwardly and a breakdown margin for reversely blocking conditions, respectively. Consequently, based on the analytical design and simulation, the novel single die bidirectional switch ultimately achieves an ultralow Ron,sp of 1.84 mΩ⋅mm2 with a bidirectional breakdown voltage (VB) of 20 V, which has a better figure of merit (FOM).

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> ). Numerical Simulation results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of the proposed SiC LDMOS is 3.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of 6.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

Comprehensive GaN-on-Si power device platform: epitaxy, device, reliability and application

In this paper, we discuss possible solutions to overcome the critical issues for GaN-on-Si power device popularization including cost competitiveness to Si power MOSFETs, system level reliability verification, and electromagnetic interference (EMI) mitigation at high switching frequency without compromising the switching loss. Both an advanced epitaxy technology and a comprehensive power device technology platform of 200 mm GaN-on-Si high electron mobility transistors (HEMTs) for mass production are presented. A novel strain engineering is reported to realize enhancement-mode HEMTs with ultralow specific on-resistance. The Si based Joint Electron Device Engineering Council reliability test, Dynamic High Temperature Operating Life, and switching accelerated lifetime test were carried out to evaluate the device reliability and lifetime. It is proved that our GaN device is robust and stable in power conversion applications. A balancing technique to mitigate EMI of the high switching frequency GaN power converter is demonstrated.

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

Analyses and Experiments of Ultralow Specific On-Resistance LDMOS With Integrated Diodes

An ultralow specific on-resistance (Ron,sp) accumulation-mode LDMOS (ALDMOS) is proposed and investigated by simulations and experiments. The proposed ALDMOS features two separated integrated diodes (SID) above the N-drift surface, which forms high density electron accumulation layer in the on-state. Meanwhile, the SID not only assists depleting the N-drift to increase the N-drift doping centration (Nd) in the off-state, but also modulates the lateral electric field to improve the breakdown voltage (BV). Thus, the proposed SID ALDMOS could achieve ultralow Ron,sp and maintain high BV simultaneously. The layout and key fabrication processes of the SID ALDMOS are demonstrated. The measured results show that the SID ALDMOS realizes a BV of 483V and Ron,sp of 29.3mΩ∙cm2, with a high FOM value of 7.96MW/cm2. Its Ron,sp is decreased by 33.7% compared with triple RESURF LDMOS at the same BV.

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation

An ultra-low specific on-resistance SOI LDMOS with stepped split protection gate L-trench (SSG LT LDMOS) is proposed. On the one hand, the stepped split protection gate (PG) not only assists in depleting the drift region but also modulates the vertical electric field. In addition, the PG diminishes the Miller capacitance, which decreasing gate-drain charge (Qgd) and switching losses of the proposed structure. On the other hand, the breakdown voltage (BV) of the proposed structure can be enhanced by the introduced L-trench (LT) and silicon-on-insulator (SOI) layer. According to the enhanced dielectric layer field (ENDIF) effect, the depletion layer and inversion layer are formed in the both sides of the LT and the SOI layer to increase BV. The LT conspicuously shortens the length of the drift region while the high BV is maintained, which further reduces the specific on-resistance (Ron,sp). The simulation results show that comparing with the conventional structure, Ron,sp is reduced by 77.2%, the figure of merit (FOM1 = BV2/Ron,sp) and BV can be increased by 486.6% and 13.7%, respectively. Meanwhile, The loss figure of merit (FOM2 = Ron,sp*Qgd) is reduced by 83.8%.

Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS

Shallow Trench Isolation (STI) and Stepped Oxide (SO) -based N-type LDMOS are simultaneously studied for the first time for low-voltage power device in this paper. Ultra-low specific on-resistance (Rsp) can be obtained in both STI- and SO-based LDMOS by scaling channel length (LCH) as well as by using the optimized drift implant. It was indicated that, to some extent, scaling LCH effectively reduces the Rsp without sacrificing breakdown voltage (BV). This is mainly ascribed to the enhanced conducting capability of channel and to the shorter cell pitch. Moreover, drift region was also studied and selected to obtain ultra-low Rsp at no cost of BV. Furthermore, scaling of gate oxide and field oxide are also demonstrated to obtain the best BV-Rsp tradeoff. Finally, it was observed that, for low-voltage LDMOS, STI-based cell exhibits slightly better BV-Rsp tradeoff, compared with SO-based LDMOS due to the shorter cell pitch. However, much better ON-state IDS-VDS characteristics can be achieved in SO-based LDMOS at small expense of Rsp. It was revealed that Rsp of 4.3 mΩ mm2 with a BV of 29.3 V are measured in our planar SO-LDMOS. This Rsp is much lower than earlier published values.

Ultralow specific ON-resistance high-k LDMOS with vertical field plate * * Project supported by the National Natural Science Foundtion of China (No.61404011), the Research and Innovation Project of Graduate Students of Changsha University of Science & Technology (No. CX2017SS25), the Scientific Research Fund of Hunan Provincial Education Department (No. 15C0034), and the Introduction of Talents Project of Changsha University of

An ultralow specific on-resistance high-k LDMOS with vertical field plate (VFP HK LDMOS) is proposed. The high-k dielectric trench and highly doped interface N+ layer are made in bulk silicon to reduce the surface field of the drift region in the VFP HK LDMOS. The gate vertical field plate (VFP) pinning in the high-k dielectric trench can modulate the bulk electric field. The high-k dielectric not only provides polarized charges to assist depletion of the drift region, so that the drift region and high-k trench maintain charge balance adaptively, but also can fully assist in depleting the drift region to increase the drift doping concentration and reshape the electric field to avoid premature breakdown. Compared with the conventional structure, the VFP HK LDMOS has the breakdown voltage of 629.1 V at the drift length of 40 μm and the specific on-resistance of 38.4 mΩ·cm2 at the gate potential of 15 V. Then the power figure of merit is 10.31 MW/cm2.

An improved SOI trench LDMOST with double vertical high-k insulator pillars * * Project supported by the National Natural Science Foundation of China (Nos. 51237001, 51607026) and the Fundamental Research Funds for the Central Universities (No. ZYGX2016J048).

An SOI trench LDMOST (TLDMOST) with ultra-low specific on-resistance (Ron,sp) is proposed. It features double vertical high-k insulator pillars (Hk1 and Hk2) in the oxide trench, which are connected to the source electrode and drain electrode, respectively. Firstly, under reverse bias voltage, most electric displacement lines produced by the charges of the depleted drift region in the source side go through the Hk1, and thus the average electric field strength under the source can be enhanced. Secondly, two additional electric field peaks are induced by the Hk1, which further modulate the electric field in the drift region under the source. Thirdly, most electric displacement lines produced by the charges of the depleted drift region in the drain side enter into the Hk2. This not only introduces one more electric field peak at the corner of the oxide trench around the Hk2, but also forms the enhanced vertical reduced surface field effect, which modulates the electric field in the drift region under the drain. With the effects of the two Hk insulator pillars, the breakdown voltage (BV) and the drift region doping concentration are significantly improved. The simulation results indicate that compared with the oxide trench LDMOST (previous TLDMOST) with the same geometry, the proposed double Hk TLDMOST enhances the BV by 86% and reduces the Ron,sp by 88%.

A novel superjunction lateral double-diffused MOS with segmented buried P-layer

A novel superjunction (SJ) lateral double-diffused MOS (LDMOS) with charge compensation to obtain an ultralow specific on-resistance (Ron,sp) is proposed in this paper. Segmented Buried P-layer(SBP)SJ LDMOS introduces segmented buried P-layer between the drift region and the substrate. The buried layer with gradual length from the source to the drain of SBP SJ LDMOS can also optimize the charge distribution of the drift region, which means it will reduce the charge compensation for SJ layer caused by the drift region under the source and increase the charge compensation for SJ layer caused by the drift region under the drain, thus achieving charge balance in the SJ layer. Compared with the conventional(Con.) SJ LDMOS at the same drift region of 33.5 μm, the breakdown voltage (BV) of the SBP SJ LDMOS is 680.5 V, enhanced by 41.7%. In addition, P-layer can also assist in depleting drift region to increase the concentrate of drift region and to decrease the Ron,sp of the device. When the gate voltage is 15 V, the Ron,sp is 42.8 mΩ cm2, reduced by 20.5% and the figure-of-merit(FOM) is 10.8 MW cm−2, increased by 152.8%.