Abstract
An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> ). Numerical Simulation results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of the proposed SiC LDMOS is 3.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of 6.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.
Highlights
Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistor (MOSFET) has attracted increasing attention and has been considered to be a great promising power switching device owing to its high switching speed and low power-loss because of the unipolar current transport mechanism and excellent electrical properties of the SiC material, such as high current density and high breakdown electric field [1]–[5]
Thanks to the development of SiC technology, the SiC complementary metal oxide semiconductor (CMOS) integrated circuits have been implemented for high-temperature applications [7]–[9]
In order to further ameliorate the trade-off relationship between the Ron,sp and the breakdown voltage (BV), and reduce the channel region resistance of the SiC lateral MOSFET, a new device structure with variation lateral doping (VLD) technique and double trench gate to reduce both drift region resistance and channel region resistance is proposed in this article
Summary
Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistor (MOSFET) has attracted increasing attention and has been considered to be a great promising power switching device owing to its high switching speed and low power-loss because of the unipolar current transport mechanism and excellent electrical properties of the SiC material, such as high current density and high breakdown electric field [1]–[5]. INDEX TERMS SiC, LDMOS, specific on-resistance, trench gate, VLD technique, breakdown voltage, lateral MOSFET.
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