Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS

Abstract

Shallow Trench Isolation (STI) and Stepped Oxide (SO) -based N-type LDMOS are simultaneously studied for the first time for low-voltage power device in this paper. Ultra-low specific on-resistance (Rsp) can be obtained in both STI- and SO-based LDMOS by scaling channel length (LCH) as well as by using the optimized drift implant. It was indicated that, to some extent, scaling LCH effectively reduces the Rsp without sacrificing breakdown voltage (BV). This is mainly ascribed to the enhanced conducting capability of channel and to the shorter cell pitch. Moreover, drift region was also studied and selected to obtain ultra-low Rsp at no cost of BV. Furthermore, scaling of gate oxide and field oxide are also demonstrated to obtain the best BV-Rsp tradeoff. Finally, it was observed that, for low-voltage LDMOS, STI-based cell exhibits slightly better BV-Rsp tradeoff, compared with SO-based LDMOS due to the shorter cell pitch. However, much better ON-state IDS-VDS characteristics can be achieved in SO-based LDMOS at small expense of Rsp. It was revealed that Rsp of 4.3 mΩ mm2 with a BV of 29.3 V are measured in our planar SO-LDMOS. This Rsp is much lower than earlier published values.