Ultra Low-k Dielectric Materials Research Articles

Surfactants as an Additive to Wet Cleaning Solutions for Plasma Etch Residue Removal: Compatibility to a Porous CVD-SiCOH Ultra Low-k Dielectric Material

With decreasing feature sizes and integration of porous low-k dielectrics within the interconnect system of integrated circuits, plasma etch residue removal becomes challenging. Plasma cleaning processes are known to degrade low-k material's properties and wet cleaning becomes a promising alternative. Using water based cleaning solutions turns out to be critical as they may not be able to wet low-energy residue surfaces or to penetrate into small features. Lowering the surface tension of the solutions will be essential and the application of surfactants is a promising approach. We investigated the static and dynamic surface tension of different surfactant solutions in DIW and their compatibility to a porous CVD-SiCOH low-k dielectric. The choice of the rinsing solution applied after surfactant treatment turned out to be essential for removing residual surfactant species. Optical, electrical and structural analysis showed that in contrast to DIW an IPA-rinse is able to remove remaining surfactant species.

Surfactants as an Additive to Wet Cleaning Solutions for Plasma Etch Residue Removal: Compatibility to a Porous CVD-SiCOH Ultra Low-k Dielectric Material

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Surface Energy and Wetting Behaviour of Plasma Etched Porous SiCOH Surfaces and Plasma Etch Residue Cleaning Solutions

The removal of plasma etch residues by wet cleaning is an alternative or additional process to plasma processes, which are known to degrade low-k and ultralow-k dielectric materials. Besides Cu/low-k compatibility wetting is an important issue for wet cleaning. Surface energy of solid and liquid is the key to understand the wetting behaviour. In this study we examined the energetic character of plasma etched/stripped solid surfaces, etch polymers and several cleaning solutions by contact angle measurements. The results show, that variations of the etching process can heavily change the energetic character of the solid. Calculating the surface energies of solid and liquid provides the possibility to make a prediction if a cleaning liquid will wet the surface which has to be cleaned.

Advanced Metrology for Porous Low-k Integration into Cu back-end Processes

Four porous ultra low-k spin-on dielectric materials from different manufacturers were characterized using X-ray reflectivity (XRR), grazing-incidence small angle X-ray scattering (GI-SAXS), transmission electron microscopy (TEM) and electrical leakage methods and their results are compared. It is shown that X-ray methods can rapidly, accurately and repeatably determine the thickness and density of the low-k film and can provide valuable insights into the pore structure, which may be able to help predict electrical leakage in the low- k material.

Time of flight secondary ion mass spectroscopy investigation of ultralow-k dielectric modifications in hydrogen and deuterium plasmas

Photoresist stripping processes based on hydrogen reductive chemistry have emerged as attractive replacements of the conventional treatments performed using O2 plasma. H2 discharges and plasma processes based on gas mixtures containing H2 provide, in fact, adequate stripping rates while reducing the chemical modifications of the porous ultralow-k (ULK) dielectric materials employed in interconnect technology. In this work the authors investigate the chemical modification of a number of organosilicate low-k dielectrics interacting with remote H2 plasma. The materials include both spin-on and plasma-enhanced chemical vapor deposited dielectrics with k, porosity, and chemical composition spanning on a broad range of values. The mechanisms of plasma∕dielectric reaction and the depth of interaction are evaluated by means of time of flight secondary ion mass spectrometry. In order to study the nature of the plasma∕dielectric interactions and the chemical modifications introduced in the ULK materials, deuterium (D2) is used to substitute for H2 in the discharge. Although the plasma-generated radicals interact strongly with the materials, negligible stoichiometry modifications are observed during exposure of silica-rich ULK materials. On the other hand, the dielectrics with higher carbon content undergo major compositional changes. The chemical damage introduced by H2-based discharges depends strongly on the formulation of the organosilicate material. The substrate temperature is also seen to affect the influx of plasma species. This acts on the extent of material modifications. Nevertheless, the nature of plasma∕dielectric interactions does not vary for processes performed in the temperature range of 200–300°C.

Investigation of the influence of different copper slurry systems on post CMP topography performance

AbstractSince the early days of copper CMP much research and development effort was put into formulation of new copper and barrier CMP slurries. Two major motivations for this effort are the improvement of process performance for currently used integration schemes and the preparation for new integration schemes using low-k and ultra low-k dielectric materials. In this paper a systematic procedure for topography investigation after copper and barrier CMP is presented. The procedure is applied to four different copper slurries in order to compare after copper and after barrier CMP topography performance. As a result of the post copper CMP topography investigations, a discussion of advantages and disadvantages of non-selective and selective barrier polish processes will be presented. To complete the discussion of potential topography correction during barrier CMP, an investigation of an observed pronounced dielectric erosion close to large metal features or within high metal density arrays with medium or high selective barrier CMP processes will be presented.

Dry Etch and Wet Clean Process Characterization of Ultra Low-k (ULK) Material Nanoglass®E

AbstractNANOGLASS®E (NGE) ultra low-k (ULK) dielectric material, with a k-value of ∼2.2, was integrated for 130 nm Cu/ULK interconnect process technology. This work deals with the characterization of reactive ion etching (RIE) and wet chemical processing of this film. Blanket films were characterized for etch rate, surface roughness, k-value change and chemical compatibility. Trench etching and post etch wet clean processes were developed and optimized enabling process integration for single damascene structures. Trench etch processes were evaluated for two etch schemes viz., etching under - photo resist and etching under hardmask. The details of each scheme will be described and advantages observed will be discussed. To evaluate effect of wet clean processes three different formulations were used. After formation of single damascene wafers, metal comb and serpentine structures were measured for metal continuity and bridging. Electrical continuity was achieved for long serpentine structures with 0.18μm/0.18μm line width/spacing. Based on voltage ramp test results the film was found to be sensitive to certain plasma etch conditions.

Electrochemical processing technologies in chip fabrication: challenges and opportunities

Cost-performance advantage of electrochemical processing technologies has enabled a paradigm shift in chip making. The dual Damascene process for Cu chip metallization and the C4 (flip-chip) technology for area array chip-package interconnection have placed electrochemical technologies among the most sophisticated fab processing technologies. These processing technologies have now been integrated into 300 mm wafer processing facilities for chip fabrication. New materials and processes are continuously being developed to meet the microprocessor industry's increasing performance and miniaturization trends. Electromigration issues, and the need for novel polishing approaches to integrate ultra low-k dielectric materials with Cu metallization are some of the immediate concerns in chip making. Development of a compliant, cost-effective Pb-free C4 chip-package interconnection is another key objective of the microelectronics industry, which is making an effort to market Pb-free products in few years. All of these developments provide ample opportunities for electrochemical processing technologies.

PTFE nanoemulsions as ultralow-k dielectric materials

Modern integrated circuits require insulating materials with a dielectric constant as low as possible in order to obtain device speed improvements through lower RC delay. We have investigated the electrical and structural properties of PTFE thin films obtained from Algoflon®-PTFE nanoemulsions, via spin coating deposition, followed by sintering. Films as thin as 160 nm with dielectric strength better than 4 MV/cm have been obtained.

Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

AbstractThe present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

Metrology Issues in Cu-Low-K Chemical Mechanical Planarization

ABSTRACTUltra low-k materials used in Cu damascene process are inherently soft and weak in nature; hence the evaluation of tribological properties of these materials is an issue of paramount importance in the field of semiconductor fabrication. Chemical Mechanical Polishing (CMP) of these films is a major challenge due to their reduced modulus and cohesive strength. The objective of this research is to develop a strong understanding of the tribological properties of Cu ultra low-k dielectric materials for successful implementation in the semiconductor devices. The Cu ultra low-k systems are polished at different conditions of load and platen rotation and their polishing behavior is compared with the standard Cu-SiO2 system. The polishing behavior of Cu and the barrier Ta material is studied in order to effectively detect the end point of the Cu CMP process. Delamination studies, post process surface characterization using scanning electron microscopy and the reliability issues of these materials also come within the scope of this study.