As processing nodes scale up, it is difficult for traditional electronic networks to supply on-chip communication efficiently due to unacceptable latency, plus power and area consumption. Alternative interconnects, such as radio frequency interconnect (RF-I) and optical interconnect, have been explored as interconnection backbones. Hybrid hierarchical architectures with both traditional interconnects and emerging interconnects have been widely adopted to get excellent trade-off between latency and power. The hybrid hierarchical architecture with a wireless/RF-I backbone is more cost-efficient and feasible due to advantages in complementary metal oxide semiconductor compatibility, compared with other alternative interconnects, and has become one of the mainstreams of chip multi-processor systems. However, how to efficiently utilize the wireless/RF-I backbone is a new challenge for designers. Based on analysis of existing typical hybrid hierarchal wireless/RF-I architectures (HHWAs), the key problems in the Design of HHWAs are proposed here, and related potential solutions are provided. In particular, strategies for resource management of wireless/RF-I are explored in detail, and different solutions are discussed. This work is expected to serve as a basis for future HHWA designs.
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