Two-stage Low Noise Amplifier Research Articles

GaN low noise amplifier MMIC with LPF and HPF noise matching

In this paper, we introduce two innovative two-stage low noise amplifiers (LNAs), each with distinct noise-matching networks. The first LNA features a low pass filter (LPF) for noise-matching in both stages, while the second uses a high pass filter (HPF) in a similar capacity. Our research focuses on evaluating the performance differences that arise from using varied matching networks within specific frequency ranges. Highlighting the critical role of appropriate network selection for optimizing gain and noise performance, our approach includes the development of two Monolithic Microwave Integrated Circuits (MMICs) using cutting-edge 0.25μm Gallium Nitride (GaN) technology. The C-band LNA, targeting a frequency range of 4–6 GHz, achieves an impressive average noise fig. (NF) of 1.5 dB and a gain of 17 dB. For the X-band range of 8–10 GHz, the LNA records a commendable average NF of 1.7 dB and a gain of 16 dB, demonstrating the effectiveness of our novel design strategies.

A 26-28 GHz, Two-Stage, Low-Noise Amplifier for Fifth-Generation Radio Frequency and Millimeter-Wave Applications.

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26-28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Bulk CMOS Low Noise Amplifier With Two Stage HPF Noise Matching Structure

In this study, a two-stage low-noise amplifier (LNA) was developed in which the noise-matching network of a high-pass filter (HPF) structure is applied to both stages. As the HPF noise matching network is used in both stages, the noise figure of the proposed LNA can be reduced compared to that of the conventional LNA. In particular, the noise figure is improved in the high-frequency region. To verify this development, a two-stage common-source LNA was implemented using 0.18-lm bulk complementary metal oxide semiconductor technology. The fabricated LNA achieved an average noise figure of 2.6 dB (minimum noise figure of 2.23 dB at 3.95 GHz) and a peak gain of 14.19 dB. In addition, the LNA has an input 1-dB compression point (IP1dB) of.12 dBm and a third-order input intercept point (IIP3) of +2.0 dBm at 3.5 GHz, consumes 16 mA with a 0.9 V supply, and has an area of 0.7 mm2.

Millimeter-Wave CMOS Low-Noise Amplifier With High Gain and Compact Footprint

For millimeter-Wave (mm-Wave) communications, this letter proposes a low-noise amplifier (LNA) topology by using gain-boosting and negative feedback techniques. In the proposed two-stage LNA, the first stage combines these two techniques to achieve a trade-off between gain and bandwidth. Following that, in the cascode structure, inductors are used to compensate for the parasitic capacitance of the transistors. To validate the proposed topology at a low cost, an mm-Wave LNA is designed and fabricated in a 180 nm CMOS process. Using two stages only, it achieves a maximum gain of 14.1 dB at 24.8 GHz, which is comparable to that of classical LNAs with three stages, and the chip footprint is reduced by 43%.

Design of a Low Cost X-Band LNA with Sub-1-dB NF for SATCOM Applications

In this article, we demonstrate a low-cost 7.25-7.75 GHz two-stage low noise amplifier with sub-1-dB noise figure for satellite communication applications. The microstrip technology on Rogers RT5880 substrate with the dielectric constant of 2.2 and thickness of 0.508 mm were utilized to develop a low noise amplifier. The printed-circuit-board technology offers a variety of profits such as being low-cost, lighter-weight and re-configurability after the manufacturing process make this technology charming for satellite communication systems for both commercial and military applications. Since the monolithic microwave integrate circuit technology provide much smaller sized circuits and high electrical performance especially at the millimeter-wave frequencies, the printed microstrip technology can be a significant rival to integrated-circuit technology with its proven reliability, easier, cheaper and faster manufacturing process, compactible electrical performance in X-band applications. Moreover, the proposed amplifier was developed with utilizing California Eastern Laboratories’ CE3512K2 transistor on Rogers-RT5880 and surface mount devices were utilized in the matching networks to reduce the size. In addition, the source-generation and interstage matching topologies were implemented to simplify the matching complexity to enhance the noise and gain. The prototype was manufactured with utilizing LPKF prototyping machine. The developed LNA exhibits a measured gain of 23.5±0.5 dB with the noise figure of less than 0.9 dB and input/output return loss better than 11.5 dB in the operating frequency bandwidth. Furthermore, the developed amplifier has a measured carrier to interference of -59 dBc and P1dB of 13 dBm at the center frequency while consuming a total DC power of 50 mW.

Area-Efficient 28-GHz Four-Element Phased-Array Transceiver Front-End Achieving 25.2% Tx Efficiency at 15.68-dBm Output Power

An area-efficient 28-GHz four-element phased-array transceiver front-end (TRx FE) is proposed in this article. Transmitter/receiver (T/R) switch, phase shifter (PS), and power combining/splitting network all use customized coupler-based structures to replace area-consuming quarter-wavelength ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4) transmission line (T-line) structures. In Tx mode, a three-stage power amplifier (PA) is designed by cascading a class-AB predriver amplifier, a deep class-AB driver amplifier, and a class-A output amplifier for high output power. In Rx mode, a two-stage low noise amplifier (LNA) is designed with a 3-bit resistive adjusting load for high dynamic range of input power. A coupler is adopted in the variable gain amplifier (VGA) to achieve constant phase during gain adjustment. The proposed TRx FE is fabricated in a 40-nm CMOS process. Measurement results show that output 1-dB compression point (OP1dB) of 14.99 dBm and saturated output power (OPsat) of 15.68 dBm with 25.2% power efficiency are achieved in each Tx element. In each Rx element, noise figure (NF) of 4.54 dB, input 1-dB compression point (IP1dB) of −10.15 dBm, and maximum gain of 26.3 dB with 56.1-mW power consumption are realized. The gain range of Rx/Tx mode is 9.9–26.3 dB/24.2–44.6 dB with a resolution of 0.3 dB and phase variation less than 2° at 28 GHz. Thanks to the area-efficient coupler-based structures, the phased-array TRx FE occupies an area of 0.42 mm2 for each element and 0.084 mm2 for total area of combiner/splitter, achieving high area efficiency for Ka-band phased-array TRx FEs.

A Gm -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

This paper presents a simple yet effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.

Two-Stage Ku-Band Graphene Low Noise Amplifier MMIC With Improved Fabrication Process

Graphene has great application potential in radio frequency (RF) electronics such as low-noise amplifier (LNA) due to its amazing electrical properties. In this work, a graphene-transfer after process was developed to fabricate two-stage graphene LNA monolithic microwave integrated circuits (MMICs) on sapphire substrate to reduce possible damage to the graphene material in the device fabrication process. Using microstrip lines, inductances, and capacitances as input–output, and interstage impedance match networks, the two-stage <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ku</i> -band graphene LNA MMIC was obtained with a 10.2 dB maximum gain at 12.7 GHz, and 4.2 dB minimum noise figure at 12.5 GHz.

A 7.2–27.3 GHz CMOS LNA With 3.51 ±0.21 dB Noise Figure Using Multistage Noise Matching Technique

A wideband low-noise amplifier (LNA) with low and flat noise figure (NF) is presented in this article. For conventional wideband noise matching, the noise performance in the high-frequency region of the entire wideband is usually deteriorated due to the frequency-dependent nature of the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) for a MOSFET. To address this issue, a novel wideband noise matching approach aiming at noise matching in high band is proposed. This approach can reduce the NF in high band at the cost of a slight NF increase in low band, eventually achieving a low and flat NF and thus a better overall noise performance for a wideband LNA. In addition, the multistage noise matching technique is employed at high frequencies to further reduce the NF caused by the second amplification stage. To validate the proposed techniques, a two-stage LNA prototype was designed and fabricated using a 65 nm CMOS process. The experimental results indicate a peak gain of 16.6 dB with a −3 dB bandwidth (BW) from 7.2 to 27.3 GHz (a fractional BW of 116%). Within the entire band of interest, the simulated NF is low and almost constant (3.3–3.4 dB), while the measured NF falls within the range of 3.30–3.72 dB. Considering the uncertainty of NF measurement, a 0.21 dB NF flatness is one of the best results among the reported millimeter-wave wideband LNAs. The measured third-order input intercept point (IIP3) is −6 dBm at 20 GHz, while the power consumption is 13.2 mW. In addition, only two passive transformers are used in this design, leading to a compact chip core area (0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

6.7–15.3 GHz, High-Performance Broadband Low-Noise Amplifier With Large Transistor and Two-Stage Broadband Noise Matching

This letter presents a fully integrated wideband, ultralow average noise figure (NF), low power consumption, compact, and electrostatic discharge protected 6.7-15.3-GHz low-noise amplifier (LNA). A peak-gain distribution technique with a large transistor and two-stage broadband noise matching technique are proposed. For verification, a two-stage common source LNA is implemented in a 65-nm bulk complementary metal-oxide-semiconductor technology. The fabricated LNA achieved an average NF of 2.08 dB and an average gain of 19.1 dB with in-band gain ripple of ±0.75 dB in the frequency range of 7.6-14.7 GHz. It has a 3-dB fractional bandwidth of 78% and the third-order input intercept point is -9.0 dBm at 10 GHz. It consumes a 16 mA at a 0.8-V supply and has an area of 0.144 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Compact low‐noise power amplifier design and implementation for millimetre wave frequencies

In this paper, we have designed and realized a two-stage low-noise power amplifier (LNPA) with resistive feedback network targeting for Ka-band compact RF front-end applications. Featuring the characteristics of both low noise and high power at the same time, the LNPA is expected to be a possible one-chip replacement of power and low noise amplifiers integrated in a conventional transceiver/receiver (T/R) module. Such configuration features size compactness while reduces implementation complexity which is of crucial importance for integration in antenna arrays with large number of antenna elements. Implemented in 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology, the LNPA, operating at 36–40 GHz, exhibits a peak gain of 15.96 dB, a minimum noise figure of 2.88 dB, a power consumption of 152 mW and a measured 1-dB compression output power of 14.92 dBm at 38 GHz, respectively. The LNPA also featured a very good linearity performance with a measured output third-order interception point (IP3) of 22.22 dBm at 38 GHz.

Design and Development of Two-stage Low-noise Amplifier (LNA) using E-pHEMT Technology for C-band Application

The low-noise amplifier (LNA) is a vital part of the radio frequency (RF) transceiver system. It amplifies weak signals with minimal distortion. The LNA performance is mainly determined by its noise figure (NF), gain, and power consumption. In this paper, the design of a 6 GHz low-noise amplifier (LNA) using enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT) technology is presented. In order to attain high gain with low S-parameters losses, a two-stage LNA configuration with single-stub matching is devised. The same bias conditions are applied to both of the LNA stages, V DS = 2.7 V and I DS = 10 mA. The LNA design is simulated and optimised by using electromagnetic (EM) software. To further improve the overall LNA performances, high impedance inductors and series resonators are implemented into the circuit. Simulated results of the designed LNA indicate a power gain, S 21 of 25.2 dB and NF of 2.4 dB at 6 GHz with 27 mW dissipation per stage. The circuit layout is fulfilled with an E-pHEMT technology (ATF-55143) on the FR4 substrate. The LNA is powered by a 3 V DC power supply.

A Ku-Band RF Front-End Employing Broadband Impedance Matching with 3.5 dB NF and 21 dB Conversion Gain in 45-nm CMOS Technology

This paper presents a K u -band RF receiver front-end with broadband impedance matching and amplification. The major building blocks of the proposed receiver front-end include a wideband low-noise amplifier (LNA) employing a cascade of resistive feedback inverter (RFI) and transformer-loaded common source amplifier, a down-conversion mixer with push–pull transconductor and complementary LO switching stage, and an output buffer. Push–pull architecture is employed extensively to maximize the power efficiency, bandwidth, and linearity. The proposed two-stage LNA employs the stagger-tuned frequency response in order to extend the RF bandwidth coverage. The input impedance of RFI is carefully analyzed, and a wideband input matching circuit incorporating only a single inductor is presented along with useful equivalent impedance matching models and detailed design analysis. The prototype chip was fabricated in 45-nm CMOS technology and dissipates 78 mW from a 1.2-V supply while occupying chip area of 0.29 mm 2 . The proposed receiver front-end provides 21 dB conversion gain with 7 GHz IF bandwidth, 3.5 dB NF, −15.7 dBm IIP 3 while satisfying &lt;−10 dB input matching over the whole input band.

Design and analysis of CMOS RF receiver front-end of LNA for wireless applications

This article deals the design and analysis of CMOS RF receiver front-end with the optimization of single-stage and two-stage low noise amplifier (LNA) for wireless applications. The low noise, high gain and better linearity for 3–10 GHz ultra wideband (UWB) wireless applications realized in 45 nm CMOS technology. The novelty of a single-ended and cascaded CMOS LNA designs for multi-standard purposeful for reconfigurable applications. The proposed LNA espouse entire circuit simulations investigation of the results in the center frequency of 3.4GHz. The admirable power gain (S21) is 32.5 dB with high reverse isolation (S12) of<−43.2dB; the preferable noise figure (NF) obtained as 0.9 dB. The perfect matching of input-output impedance for stability has measured to significantly input-output reflection coefficients S11=−11.6dB,S22=−10.0dB respectively while consuming only 11.8 mW from a 1 V supply.

Two-stage S-Band LNA Development Using Non-Simultaneous Conjugate Match Technique

This paper presents the development of a two-stage low noise amplifier (LNA) operating at the S-band frequency that is implemented using the non-simultaneous conjugate match (NSCM) technique. The motivation of this work was to solve the issue of the gain of LNAs designed using the most commonly used technique, i.e. simultaneous conjugate match (SCM), which often produce an increase of other parameter values, i.e. noise figure and voltage standing wave ratio (VSWR). Prior to hardware implementation, the circuit simulation software Advanced Design System (ADS) was applied to design the two-stage S-band LNA and to determine the desired trade-off between its parameters. The proposed two-stage S-band LNA was deployed on an Arlon DiClad527 using a bipolar junction transistor (BJT), type BFP420. Meanwhile, to achieve impedances that match the two-stage S-band LNA circuit, microstrip lines were employed at the input port, the interstage, and the output port. Experimental characterization showed that the realized two-stage S-band LNA produced a gain of 22.77 dB and a noise figure of 3.58 dB at a frequency of 3Â GHz. These results were 6.1 dB lower than the simulated gain and 0.76 dB higher than the simulated noise figure respectively.

915-MHz Continuous-Wave Doppler Radar Sensor for Detection of Vital Signs

A miniaturized continuous-wave Doppler radar sensor operating at 915 MHz to remotely detect both respiration and heart rate (beats per minute) is presented. The proposed radar sensor comprises a front-end module including an implemented complementary metal-oxide semiconductor low-noise amplifier (LNA) and fractal-slot patch antennas, whose area was reduced by 15.2%. The two-stage inverter-based LNA was designed with an interstage capacitor and a feedback resistor to acquire ultrawide bandwidth. Two operating frequencies, 915 MHz and 2.45 GHz, were analyzed with regard to path loss for efficient operation because frequency affects detection sensitivity, reflected signal power from the human body, and measurement distance in a far-field condition. Path-loss calculation based on the simplified layer model indicates that the reflected power of the 915 MHz radar could be higher than that of the 2.45 GHz radar. The implemented radar front-end module excluding the LNA occupies 35 × 55 mm2. Vital signs were obtained via a fast Fourier transform and digital filtering using raw signals. In an experiment with six subjects, the respiration and heart rate obtained at 0.8 m using the proposed radar sensor exhibited mean accuracies of 99.4% and 97.6% with respect to commercialized reference sensors, respectively.

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low-noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two-stage low-noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two-stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre-determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures-of-merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka-band (26.5-31.5 GHz) and K-band (20.0-24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka-band and K-band version. Input and output matching are typically better than 12 and 15 dB.

A correlation noise spectrometer for flicker noise measurement in graphene samples

We present a high-resolution digital correlation spectrum analyzer for the measurement of low frequency resistance fluctuations in graphene samples. The system exploits the cross-correlation method to reject the amplifiers’ noise. The graphene sample is excited with a low-noise DC current. The output voltage is fed to two two-stage low-noise amplifiers connected in parallel; the DC signal component is filtered by a high-pass filter with a cutoff frequency of 34 mHz. The amplified signals are digitized by a two-channel synchronous ADC board; the cross-periodogram, which rejects uncorrelated amplifiers’ noise components, is computed in real time. As a practical example, we measured the noise cross-spectrum of graphene samples in the frequency range from 0.153 Hz to 10 kHz, both in two- and four-wire configurations, and for different bias currents. We report here the measurement setup, the data analysis and the error sources.

Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm 2 while the total chip area, including the pad frame, is 1.55 × 0.85 mm 2 .