Two-stage Amplifier Research Articles

A very low-power discrete-time delta-sigma modulator for wireless body area network

This paper proposes a very low-power discrete-time delta-sigma modulator (DTDSM) for the wireless body area network (WBAN) which deals with biomedical signals. The first stage integrator is optimized using correlated double sampling technique and is implemented using a high-gain designed telescopic operational transconductance amplifier (OTA) in order to maintain the proposed second-order DTDSM high resolution. In order to keep both stage integrators active and prevent ENOB loss, a very low power two-stage charge-steering amplifier is employed in the second stage integrator which leads to a power efficient design. Due to not high but enough voltage-gain of this type of amplifier, the proposed charge-steering-based integrator leads to a negligible loss of ENOB in comparison to passive integrators with no voltage gain which are commonly used in the second stage to reduce the total power. In fact, due to the combination of a high-gain OTA in first stage integrator and a low-power charge-steering amplifier in second stage, compromise between high resolution and low power consumption will be depicted.The proposed DTDSM is designed for a signal bandwidth of 50 kHz with an oversampling ratio of 128 for implantable biomedical devices in the MICS band. Simulations are done using TSMC 180 nm technology at a 1.8 V power supply. Simulation results illustrate that the designed modulator achieves an SNR of 56 dB which is equal to 9 bits of ENOB that is in the desired range for biomedical signals. The power consumption of this modulator is only 142 μW at a 12.5 MHz sampling frequency.

28-nm CMOS 공정을 이용한 W-대역 레이다 송신기용 전력증폭기 설계

In this paper, we present a W-band power amplifier using a 28-nm CMOS process for radar applications. The designed amplifier consists of a two-stage driver amplifier and last-stage power amplifier. The driver amplifier uses a differential common-source topology, and the power amplifier adopts a differential cascode topology. Both the driver amplifier and power amplifier utilize the neutralization technique at the common-source stage for stability and sufficient power gain. Each interstage of the amplifier used a transformer for impedance matching. The W-band signal applied to the first driving amplifier is supplied 14 GHz to 16 GHz external signal source multiplied by 6 using the internal multiplier, the power amplifier achieved 14.9 dBm output power, and the 3-stage amplifier consumed 262 mW of DC power. The 1 dB-bandwidth is 10 GHz from 85 GHz to 95 GHz. The core size of the 3-stage amplifier is 110 μm × 300 μm.

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique

This paper describes a 12-bit 1.25-GS/s RF sampling pipelined analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. To achieve high-speed and high-resolution conversion, a two-stage push-pull residue amplifier powered by a dual-supply is employed. A left half-plane (LHP) zero is generated through the coupling capacitance to expand the bandwidth and an inverter-based auxiliary amplifier is used to improve the gain and simplify the design. In addition, the proposed residue amplifier achieves a stable closed-loop characteristic without adding compensation capacitance, which greatly saves the area and improves the power efficiency. With an 18 MHz and 2 Vpp input signal, the SNDR is 61.5 dB, the SFDR is 70.2 dB. And the SNDR and SFDR are greater than 58 dB and 69 dB over the entire Nyquist bandwidth while the power consumption is 45.6 mW.

Large-Signal Equivalent-Circuit Model of Asymmetric Electrostatic Transducers

This article presents a circuit model that is able to capture the full nonlinear behavior of an asymmetric electrostatic transducer whose dynamics are governed by a single degree of freedom. Effects such as stress-stiffening and pull-in are accounted for. The simulation of a displacement-dependent capacitor and a nonlinear spring is accomplished with arbitrary behavioral sources, which are a standard component of circuit simulators. As an application example, the parameters of the model were fitted to emulate the behavior of an electrostatic MEMS loudspeaker whose finite-element (FEM) simulations and acoustic characterisation where already reported in the literature. The obtained waveforms show good agreement with the amplitude and distortion that was reported both in the transient FEM simulations and in the experimental measurements. This model is also used to predict the performance of this device as a microphone, coupling it to a two-stage charge amplifier. Additional complex behaviors can be introduced to this network model if it is required.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Automated Design of Analog Circuits Using Reinforcement Learning

Analog and mixed-signal (AMS) blocks are often a crucial and time-consuming part of System-on-Chip (SoC) design, primarily due to a manual circuit and layout iterations. Existing automated solutions for selecting circuit parameters for a given target specification are often not efficient, accurate, or reliable. In order for an automated sizing tool to be practical, we posit that it must: 1) return valid results for a large range of target specifications; 2) understand where and why it is unable to meet certain specifications; 3) consider true layout parasitic simulations for complete end-to-end design; and 4) be automated, allowing most of the design effort to fall on the tool. In this article, we address these critical points by establishing an automated reinforcement learning framework, AutoCkt, by 1) successfully deploying it on a complex two-stage transimpedance amplifier and two-stage folded cascode with biasing in the 16-nm FinFet technology; 2) implementing a new combined distribution deployment algorithm to improve efficiency; 3) analyzing in-depth the efficacy of the trained agent; and 4) demonstrating the functionality of this tool when considering a topology that is highly sensitive to layout parasitics. Our algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, up to 38X more efficient than prior work. In addition, our tool averages just four parasitic simulations obtained by using the Berkeley Analog Generator, to achieve a target specification post-layout for the folded cascode. AutoCkt successfully generates LVS-passed designs with validation in process corner variation results.

MmWave Spatial–Temporal Single Harmonic Switching Transmitter Arrays for High Back-Off Beamforming Efficiency

This paper presents a spatial-temporal single harmonic switching (STHS) transmitter array architecture with enhanced efficiency in the power back-off (PBO) region. STHS is an electromagnetic and circuit co-designed and jointly optimized transmitter array that realizes beamforming and back-off power generation at the same time. The temporal dimension is originally added in STHS to achieve back-off efficiency enhancement, which can be combined with conventional power back-off enhancement methods such as Doherty amplifiers and envelope tracking. The design is validated through a simulation of a two-stage power amplifier in 65-nm CMOS at 77 GHz, which achieves a peak drain efficiency (DE) of 24.2%, a 22% DE at 3-dB PBO, 16% DE at 6-dB PBO, and 10.2% at 9-dB PBO. The efficiency exhibits a 57% improvement at 3-dB PBO, 100% improvement at 6-dB PBO, and 190% improvement at 9-dB PBO compared with class A/B amplifier.

A Reference Source Circuit Design for Voltage Controlled Oscillator Chips

The basic principle and typical structure of the bandgap voltage reference source are introduced in detail in this paper. The performance index of the bandgap voltage reference is analyzed. The core circuit of a bandgap voltage reference source with good temperature characteristics and a high power supply rejection ratio (PSRR) is designed, in which a two-stage differential operational amplifier with a buffer stage is used, a start-up circuit without a capacitor is used to reduce the start-up time, and a common beta multiplication self-bias circuit is used to attenuate the effects of the power supply voltage. It is shown from the final HSPICE simulation results that the reference voltage temperature coefficient is approximately 7 ppm/°C within the range of -20 to 80°C in temperature, and the average PSRR can reach more than −56 dB within the range of 1 Hz to 10 kHz in frequency.

Self-heating of cryogenic high electron-mobility transistor amplifiers and the limits of microwave noise performance

The fundamental limits of the microwave noise performance of high electron-mobility transistors (HEMTs) are of scientific and practical interest for applications in radio astronomy and quantum computing. Self-heating at cryogenic temperatures has been reported to be a limiting mechanism for the noise, but cryogenic cooling strategies to mitigate it, for instance, using liquid cryogens, have not been evaluated. Here, we report microwave noise measurements of a packaged two-stage amplifier with GaAs metamorphic HEMTs immersed in normal and superfluid 4He baths and in vacuum from 1.6 to 80 K. We find that these liquid cryogens are unable to mitigate the thermal noise associated with self-heating. Considering this finding, we examine the implications for the lower bounds of cryogenic noise performance in HEMTs. Our analysis supports the general design principle for cryogenic HEMTs of maximizing gain at the lowest possible power.

Sensitive ultrawideband transparent PVDF-ITO ultrasound detector for optoacoustic microscopy

An ultrasound detection scheme based on a transparent polyvinylidene-fluoride indium-tin-oxide (PVDF-ITO) piezoelectric film is developed for ultrawideband sensitive detection of optoacoustic (OA) signals down to a noise equivalent pressure (NEP) of 8.4 Pa over an effective detection bandwidth extending beyond 30 MHz. The high signal-to-noise ratio and low noise performance are facilitated by employing a two-stage amplifier structure. The PVDF-ITO detector is directly mounted on a commercial high numerical aperture objective lens of a scanning optical resolution OA microscopy system to obtain submicron resolution images without signal averaging, as demonstrated both in phantoms and in vivo measurements in mice. The transparent detection scheme further allows for the OA imaging modality to be easily integrated with other imaging techniques for diverse multi-modal biomedical imaging investigations.

A high-gain two-stage amplifier using low-temperature poly-si oxide thin-film transistors with a Corbino structure

This paper proposes a complementary metal–oxide–semiconductor (CMOS) amplifier using low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The Corbino structure used in the proposed amplifier has a higher output resistance than conventional amplifiers. The proposed circuit is composed of two CMOS inverters, one CMOS switch, and one input capacitor. It was possible to determine the operating point where the voltage gain could be kept high, regardless of the device variation, by shorting the gate input and output of the first amplifier. The alternating current component of the input signal was increased because the input signal was transferred to the first amplifier via the capacitor. The function of the second amplifier was to increase the total voltage gain. When a peak-to-peak voltage sine wave of 2 mV was applied at a frequency lower than 500 Hz, the proposed circuit showed an average voltage gain of 60.6 dB, which is the highest among the previously published TFT amplifiers.

An ultra-fast low-noise preamplifier for Low Gain Avalanche Detectors

The Low Gain Avalanche Detector (LGAD) is a novel Silicon detector with precise timing and fast response. To study the transient response of LGADs, we need to obtain the detector signal using Transient Current Technique (TCT), for which a preamplifier with high bandwidth and low noise is required. Currently, the most widely used preamplifier board in the LGAD community is developed by University of California, Santa Cruz (UCSC). In this paper, we will introduce a newly designed LGAD preamplifier board. Compared with the UCSC board, the performance has been fully improved. The board contains a transimpedance amplifier and two-stage voltage amplifiers. The total charge gain of our preamplifier reaches 20.58 mV ns/fC, with good linearity in the input dynamic range of [0.7 fC, 66 fC]. The −3-dB bandwidth is about 870 MHz, meeting the demands of LGAD amplification. We conducted 90Sr β-scope tests using our preamplifiers and HPK 3.1 single sensors. The equivalent noise charge at 20 °C is 0.27 fC. The jitter contributed by our preamplifier is about 7.12 ps. The results show that our single-channel preamplifier has lower noise and better time resolution than the UCSC boards. Besides, a 9-channel preamplifier board is developed for multi-pad LGAD readout. All channels have good uniformity and low noise. Our preamplifier boards can be well applied in β-scope or laser-scanning TCT tests of LGADs.

Design and test of a compact large-stroke dual-drive linear-motion system

This paper presents the design, modelling, analysis, and test of a piezo-actuated dual-drive linear motion system, capable of millimeter stroke with nanometer resolution. The primary actuator is a two-stage bridge-type amplifier with hybrid flexure hinges, which is driven by a piezo-stack actuator and generates output stroke greater than 6 mm. The micro actuation is directly driven by an extra piezo-stack to achieve resolution of 20 nm. A very large amplification ratio of 91 is achieved, which implies not only large stroke but also compactness. An inherent characteristic for the multi-stage compliant displacement amplifier, ‘kick-back’ phenomenon, is first analyzed and eliminated by using the stiffness distribution method. The architectural parameters are optimized by genetic algorithm to find the trade-off among natural frequency, stroke and stiffness ratio. The optimized design was then fabricated and tested. The superiority of the proposed system is remarkable compared with other similar works. The concept and approach outlined are generic and can be extended to this class of actuators.

Broadband 100-W Ka-Band SSPA Based on GaN Power Amplifiers

In this letter, we report on the realization of a two-stage 16-way solid-state power amplifier (SSPA) in the <i>Ka</i>-band. To this end, we describe the design of a high-power amplifier (HPA) in a 100-nm gallium nitride (GaN) process and its integration into a split-block waveguide module. The PA module achieves an output power of more than 7.6 W between 28 and 39 GHz. In conjunction with 16 of these PA modules, we then employed a custom low-loss radial splitter and combiner to create a compact SSPA system. The two-stage SSPA configuration exhibits a small-signal gain of up to 44 dB and a peak output power of 127 W at 31 GHz in 5 dB of gain compression. Furthermore, we measured output power of close to 100 W and state-of-the-art efficiency values of more than 19&#x0025; between 28 and 38 GHz. To our knowledge, this is the most broadband high-power SSPA demonstrated so far in this frequency range.

Building a post-layout simulation performance model with global mapping model fusion technique

Building a post-layout simulation performance model is essential in closing the loop of analog circuits, but it is a challenging task because of the high-dimensional space and expensive simulation cost. To facilitate efficient modeling, this paper proposes a Global Mapping Model Fusion (GMMF) technique. The key idea of GMMF is to reuse the schematic-level model trained by the Artificial Neural Network (ANN) algorithm, and combine it with few mapping coefficients to build the post-simulation model. Furthermore, as an efficient global optimization algorithm, differential evolution is applied to determine the optimal mapping coefficients with few samples. In GMMF, only a small number of mapping coefficients are unknown, so the number of post-layout samples needed is significantly reduced. To enhance practical utility of the proposed GMMF technique, two specific mapping relations, i.e., linear or weakly no-linear and nonlinear, are carefully considered in this paper. We conduct experiments on two topologies of two-stage operational amplifier and comparator in different commercial processes. All the simulation data for modeling are obtained from a parametric design framework. A more than 5× runtime speedup is achieved over ANN without surrendering any accuracy.

Enhancing Dynamic Bandwidth of Amplified Piezoelectric Actuators by a Hybrid Lever and Bridge-Type Compliant Mechanism

Ongoing interests in high-speed precision actuation continuously sparks great attention on developing fast amplified piezoelectric actuators (APAs) with compliant mechanisms. A new type of APA with enhanced resonance frequency is herein reported based on a hybrid compliant amplifying mechanism. A two-stage displacement flexure amplifier is proposed by synthesizing the lever-type and semi bridge-type compliant mechanisms in a compact configuration, promising to a well tradeoff between the displacement amplification ratio and dynamic bandwidth. The static and dynamic performances are experimentally evaluated. The resonance frequency of 2.1 kHz, displacement amplification ratio of 6, and step response time of around 0.4 ms are realized with a compact size of 50 mm × 44 mm × 7 mm. Another contribution of this paper is to develop a comprehensive two-port dynamic stiffness model to predict the static and dynamic behaviors of the compliant amplifier. The modeling approach presented here differs from previous studies in that it enables the traditional transfer matrix method to formulate both the kinetostatics and dynamics of compliant mechanisms including serial-parallel branches and rigid bodies.

Monolithic integrated two-stage cascaded SOA-PIN receiver for high-speed optical wireless communication.

Monolithic integrated receivers are highly desired due to the potential of mass production and the reduction of device size and cost. In this Letter, a monolithic integrated optical wireless communication (OWC) receiver with optical preamplifiers is designed, fabricated, and investigated to achieve high sensitivity based on photonic integration technology. The proposed receiver consists of one waveguide PIN photodetector integrated with two semiconductor optical amplifiers (SOAs). Compared with using a one-stage optical amplifier, using two independent SOAs as a two-stage amplifier offers the advantage of optimizing the noise figure of each amplifier independently by tuning their injection currents, which leads to the reduction of the total noise and an improvement of the receiver sensitivity. The achieved sensitivity for a 10-Gb/s OOK signal with 10-dBm launch power at 1550-nm wavelength by using the designed receiver is up to -27.5 dBm at a bit-error-ratio (BER) level of 3.1×10-3 over a 0.9-m indoor free-space link. The experimental results show the potential to achieve a high-speed OWC link with high sensitivity by using a cascaded SOA/PIN monolithic integrated receiver.

Single-Cycle, Multigigawatt Carrier–Envelope-Phase-Tailored Near-to-Mid-Infrared Driver for Strong-Field Nonlinear Optics

A short-pulse, frequency-tunable idler-wave output of a two-stage optical parametric amplifier is compressed in a gas-filled antiresonance-guiding hollow-core photonic-crystal fiber to yield ultrashort field waveforms of near-to-mid-infrared (near-IR/mid-IR) radiation with a pulse energy of up to 28 μJ, a peak power of up to 4 GW, and a pulse width smoothly tunable, via gas-pressure adjustment inside the gas-filled hollow fiber, all the way down to a single field cycle at ≤6.6 fs. With the active carrier–envelope phase (CEP) stabilization extended to its entire multioctave bandwidth, the single-cycle near-to-mid-IR fiber output is CEP-stable within 140 mrad and can be finely tailored toward a desired CEP profile. High-order harmonics generated by such pulses in solids exhibit clear signatures of strong-field single-cycle nonlinear optics. Well-resolved harmonic peaks, which dominate the visible–ultraviolet spectrum of the nonlinear-optical response of a solid driven by multicycle near-to-mid-IR pulses, tend to broaden and merge together as the driver pulse width approaches the field cycle, eventually giving rise to visible–ultraviolet supercontinua as a signature of single-cycle light–matter interactions.

28-nm CMOS 공정을 이용한 Ka-Band 수신기 설계

This study presents a Ka-band direct-conversion receiver using a 28-nm CMOS (Complimentary Metal Oxide Semiconductor) process for radar applications. The designed receiver includes a LNA (Low-Noise Amplifier), Mixer, and Baseband amplifier. The LNA adopts a two-stage cascode amplifier structure. Then, the mixer is a single-balanced passive mixer with low flicker noise. At the end, the baseband amplifier is a transimpedance amplifier with fat FET (Field-Effect-transistor) for low flicker noise and current-mode operation of the mixer. The LO (Local Oscillator) signal for driving the mixer is supplied externally. The performance of the receiver is tested using on-wafer probing and an air test is performed by integrating a microstrip antenna. The total conversion gain, noise figure, and 3 dB bandwidth are 28 dB, 6.1 dB, and 6 GHz, respectively. The chip size is 0.320 mm2.

Design of an Ultra-Compact 60-GHz Bi-Directional Amplifier in 65-nm CMOS

This letter presents an ultra-compact two-stage 60-GHz differential bi-directional amplifier (DBA) design in a 65-nm CMOS process. To satisfy the stability and gain requirements, a differential neutralized bi-directional common-source gain cell combined with the cross-coupled gm-boosting technique is proposed. In addition, a layout-symmetrical coupled line transformer is used as the inter-stage matching network to achieve broadband operation, reducing insertion loss and ensuring identical responses in both forward/backward modes. The proposed DBA achieves a peak gain of 16.1 dB with a 3-dB bandwidth of 15 GHz (52-67 GHz), maximum OP <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $_{{1 ,,dB}}$ </tex> </formula> of 5.1 dBm, <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $P_{{SAT}}$ </tex> </formula> of 9.6 dBm, a peak PAE of 11.5% at 62 GHz, respectively, consuming 70 mW from a power supply of 1.2 V. The circuit core occupies an ultra-compact area of only 0.0675 mm².