Two-dimensional Device Simulation Research Articles

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.

Dual direction SCR with deep well structure for high voltage ESD in communication bus

In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device’s fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

Theoretical studies of silicon hetero-junction solar cells with rib structure

The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. To provide thinned wafers that have adequate mechanical strength, we proposed a thin Si wafer-based solar cell that uses a rib structure in a previous work. We formed a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength and fabricated the conventional Si hetero-junction structure by depositing hydrogenated amorphous Si on the wafer. For optimum design of the rib structure cell, we analytically studied the effect of rib dimensions on wafer strength and photovoltaic characteristics. A simplified structural analysis was performed to investigate the mechanical strength of the rib structure for various rib dimensions. Photovoltaic characteristics of rib structure silicon hetero-junction cells were also studied by a two-dimensional device simulator to understand the effect of rib dimensions. From these analyses, we theoretically demonstrated that the rib structure cell is a very good candidate to realize thin wafer Si solar cell, and can achieve both mechanical strength and electrical performance of thin Si solar cells.

Breakdown Voltage Enhancement in AlGaN/GaN High-Electron Mobility Transistor by Optimizing Gate Field-Plate Structure.

We optimize various gate head structures to improve breakdown voltage characteristics of AlGaN/GaN high-electron mobility transistors by a two-dimensional device simulator based on a T-shaped gate-connected field-plate. Field-plates (FPs) alleviate electric field spikes near the gate and drain-side overlapping edges, which eventually disperse electron avalanche and charge trapping effects. Hence, the more uniform electric field distribution provides improved breakdown voltage of the device. Multiple configurations, such as extension of the FP towards the source or drain, and symmetric extension, were investigated and compared. The best results were acquired when the FP was extended towards the drain, with an optimum length of 2 μm, which produced maximum breakdown voltage of 224 V and maximum transconductance of 132.5 mS/mm. Also, the optimum Si₃N₄ passivation layer thickness based on a T-shaped gate-connected FP structure was 50 nm.

Simulation of dark current characteristics of type-II InAs/GaSb superlattice mid-wavelength infrared p–i–n photodetector

For photosensitive devices such as infrared (IR) photodetectors, dark current is an important mechanism limiting the performance because it causes a decrease in the signal-to-noise ratio and the responsivity. The main objective of this work is to understand and analyze the InAs/GaSb type-II superlattice (SL) IR photodiode using a device simulator especially focusing on the dark current characteristics. Physical parameters such as the effective density of states and the effective masses are extracted from the k·p band calculation, and included into a two-dimensional device simulator based on the drift-diffusion model. Simulation results demonstrate that the leakage current of the IR photodiode depends on the SL thickness ratio even with the same cut-off wavelength. In the low reverse bias conditions, the “InAs-rich” SL detectors exhibit smaller dark current than the “GaSb-rich” ones, which originates from the difference in the intrinsic carrier density. On the other hand, under the higher voltage and the higher doping level, the larger effective mass of “GaSb-rich” SL can suppress the dark current caused by the tunneling-related leakage mechanisms.

Analysis of drain current saturation behaviour in GaN polarisation super junction HFETs

The magnitude of saturation current in a power device significantly impacts its short-circuit capability. In conjunction with the unprecedented miniaturisation that gallium nitride (GaN) offers, there is a compelling rationale to examine this critical parameter in GaN transistors for thermally stable and reliable power converter applications. This study presents a comprehensive analysis of the physical behaviour that yields intrinsically low drain current saturation in GaN polarisation super junction heterojunction field-effect transistors (PSJ HFETs). The analysis in this work has been performed using electrical characterisation data of conventional and PSJ HFETs, supported by physics-based two-dimensional device simulations. Insight is gained on the differing device architecture-dependent mechanisms that determine the magnitude of drain current density in both types of devices when biased in the saturation region.

Influence of barrier layer’s height on the performance of Si quantum dot solar cells

We investigated the influence of the barrier layer height in silicon quantum dot superlattice (Si-QDSL) solar cells on the cell performance by two-dimensional device simulation taking into account the quantum size effect. Although at Si-QD diameters (d) of 5 and 10 nm better cell performance was obtained as the barrier height increased, in the case of d = 3 nm, the efficiency decreased as the barrier height increased. Further investigation showed that the band mismatch at the interface between Si-QDSL and the n-type layer degraded open-circuit voltage (Voc) at d = 3 nm. After the optimization of the physical properties of the n-type layer, Voc was improved to 1.43 V and the bandgap-Voc (Woc) offset became about 0.4 V, suggesting that the band mismatch is the significant factor for the Voc loss. From these results, it was found that careful selection of n- or p-type materials is necessary when the strong quantum confinement effect occurs in Si-QDSL.

Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study

In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to realize different logic functions and investigated using two-dimensional device simulations. It is shown that a single DGTFET can realize logic functions, such as AND, OR, NAND, and NOR by biasing the two gates independently. The key elements in obtaining different logic functions using a DGTFET are employing a gate–source overlap and choosing an appropriate silicon body thickness. Furthermore, it is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination

We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that VO2+ were generated near the drain side of TFT, but the hump was not induced when VO2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because VO2+ were created near the drain side, then were migrated to the source side of the TFT.

Control of short-channel effects in InAlN/GaN high-electron mobility transistors using graded AlGaN buffer

A graded AlGaN buffer is designed to realize the p-type buffer by inducing polarization-doping holes. Based on the two-dimensional device simulator, the effect of the graded AlGaN buffer on the direct-current (DC) and radio-frequency (RF) performance of short-gate InAlN/GaN high-electron mobility transistors (HEMTs) are investigated, theoretically. Compared to standard HEMT, an enhancement of electron confinement and a good control of short-channel effect (SCEs) are demonstrated in the graded AlGaN buffer HEMT. Accordingly, the pinched-off behavior and the ability of gate modulation are significantly improved. And, no serious SCEs are observed in the graded AlGaN buffer HEMT with an aspect ratio (LG/tch) of about 6.7, much lower than that of the standard HEMT (LG/tch = 13). In addition, for a 70-nm gate length, a peak current gain cutoff frequency (fT) of 171 GHz and power gain cutoff frequency (fmax) of 191 GHz are obtained in the grade buffer HEMT, which are higher than those of the standard one with the same gate length.

2-D modeling and analysis of short-channel behavior of a front high-K gate stack triple-material gate SB SON MOSFET

This paper presents the 2-D analytical modeling of a front high-K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson’s equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

Simulation Study of Front-Lit Versus Back-Lit Si Solar Cells

Continuous efforts are being made to improve the efficiency of Si solar cells, which is the prevailing technology at this time. As opposed to the standard front-lit solar cell design, the back-lit design suffers no shading loss because all the metal electrodes are placed on one side close to the pn junction, which is referred to as the front side, and the incoming light enters the denuded back side. In this study, a systematic comparison between the two designs was conducted by means of computer simulation. Medici, a two-dimensional semiconductor device simulation tool, was utilized for this purpose. The 0.6 μm wavelength, the peak value for the AM-1.5 illumination, was chosen for the incident photons, and the minority-carrier recombination lifetime (τ), a key indicator of the Si substrate quality, was the main variable in the simulation on a p-type 150 μm thick Si substrate. Qualitatively, minority-carrier recombination affected the short circuit current (Isc) but not the opencircuit voltage (Voc). The latter was most affected by series resistance associated with the electrode locations. Quantitatively, when τ ≥ 500 μs, the simulation yielded the solar cell power outputs of 20.7 mW·cm−2 and 18.6 mW·cm−2, respectively, for the front-lit and back-lit cells, a reasonable 10 % difference. However, when τ < 500 μs, the difference was 20 % or more, making the back-lit design less than competitive. We concluded that the back-lit design, despite its inherent benefits, is not suitable for a broad range of Si solar cells but may only be applicable in the high-end cells where float-zone (FZ) or magnetic Czochralski (MCZ) Si crystals of the highest quality are used as the substrate.

Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration.

Utilizing Schottky barriers to suppress short-channel effects in organic transistors

Transistors with short channel lengths exhibit profound deviations from the ideally expected behavior. One of the undesired short-channel effects is an enlarged OFF current that is associated with a premature turn on of the transistor. We present an efficient approach to suppress the OFF current, defined as the current at zero gate source bias, in short-channel organic transistors. We employ two-dimensional device simulations based on the drift-diffusion model to demonstrate that intentionally incorporating a Schottky barrier for injection enhances the ON-OFF ratio in both staggered and coplanar transistor architectures. The Schottky barrier is identified to directly counteract the origin of enlarged OFF currents: Short channels promote a drain-induced barrier lowering. The latter permits unhindered injection of charges even at reverse gate-source bias. An additional Schottky barrier hampers injection for such points of operations. We explain how it is possible to find the Schottky barrier of the smallest height necessary to exactly compensate for the premature turn on. This approach offers a substantial enhancement of the ON-OFF ratio. We show that this roots in the fact that such optimal barrier heights offer an excellent compromise between an OFF current diminished by orders of magnitude and an only slightly reduced ON current.

Simulation study of InAlN/GaN high-electron mobility transistor with AlInN back barrier**Project supported by the Natural Science Foundation of Hebei Province, China (Grant No. F2013202256).

In this work, we use a 3-nm-thick Al0.64In0.36N back-barrier layer in In0.17Al0.83N/GaN high-electron mobility transistor (HEMT) to enhance electron confinement. Based on two-dimensional device simulations, the influences of Al0.64In0.36N back-barrier on the direct-current (DC) and radio-frequency (RF) characteristics of InAlN/GaN HEMT are investigated, theoretically. It is shown that an effective conduction band discontinuity of approximately 0.5 eV is created by the 3-nm-thick Al0.64In0.36N back-barrier and no parasitic electron channel is formed. Comparing with the conventional InAlN/GaN HEMT, the electron confinement of the back-barrier HEMT is significantly improved, which allows a good immunity to short-channel effect (SCE) for gate length decreasing down to 60 nm (9-nm top barrier). For a 70-nm gate length, the peak current gain cut-off frequency (fT) and power gain cut-off frequency (fmax) of the back-barrier HEMT are 172 GHz and 217 GHz, respectively, which are higher than those of the conventional HEMT with the same gate length.

Permittivity and temperature effects on rectification performance of self-switching diodes with different geometrical structures using two-dimensional device simulator

Characterization on an InGaAs-based self-switching diode (SSD) using technology computer aided design (TCAD) aimed for optimizing the electrical rectification performance of the device is reported. The rectifying performance is mainly contributed by a parameter known as the curvature coefficient which is derived from the current-voltage (I-V) behavior of the device. As such, the curvature coefficient of SSD was analyzed in this work, not only by varying the device’s geometrical structure, but also by implementing different dielectric relative permittivity of the device’s trenches, ranging from 1.0 to 10. Furthermore, the simulations were performed under temperature range of 300–600K. The results showed that increased temperature degraded the SSD’s rectifying performance due to increased reverse current which can deteriorate the nonlinearity of the device’s I-V characteristic. Moreover, an improved curvature coefficient can be achieved using silicon dioxide (∼3.9) as the SSD trenches. The cut-off frequency of SSD with zero-bias curvature coefficient of ∼30V−1 attained in this work was approximately 80GHz, operating at unbiased condition. The results obtained can assist the design of SSD to efficiently operate as rectifiers at microwave and terahertz frequencies.

The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT

The electrical characteristics of a low-temperature polycrystalline silicon thin-film transistor (TFT) with a source-contacted light shield (SCLS) are observed and analyzed. Compared with that of a conventional TFT without a light shield (LS), the on-current of the TFT with an SCLS is lower because the SCLS blocks the fringing electric field from the drain to the active layer. Furthermore, the gate-to-source capacitance (Cgs) of the TFT with an SCLS in the off and saturation regions is higher than that of a conventional TFT, which is due to the gate-to-LS capacitance (Cg-LS). The electrical characteristics of the TFT with an SCLS are thoroughly investigated by two-dimensional device simulations, and a semi-empirical Cg-LS model for SPICE simulation is proposed and verified.

Investigation of the drain-induced barrier lowering of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length

ABSTRACTThe transistor size needs to be reduced as the pixel density of the organic light-emitting diode (OLED) display increases for mobile application. Drain-induced barrier lowering (DIBL), however, hinders the further channel length reduction of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which leads to severe mura of the OLED display for the low-gray level. The two-dimensional device simulation analysis showed that the potential energy barrier for the holes in the p-channel TFT decreases as the drain voltage intensifies from −1 to −10 V. The barrier lowering becomes severe as the channel length is reduced from 5 to 2 µm, but it does not have any noticeable dependency on the grain size variation from 0.3 to 0.5 µm. It was also found that the degree of DIBL varies considerably depending on the position of the grain boundary even for the same grain size, as the channel length is reduced. It was determined from the analysis that was conducted in this study that the deviation of the subthreshold current for the variation of the grain size and the grain boundary location increases 64 times as the channel length is reduced from 5 to 2 µm.

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.