Two-dimensional Device Simulation Research Articles

Gate length related transfer characteristics of GaN-based high electron mobility transistors

The measured drain current of GaN high electron mobility transistor (HEMT) shows a saturated characteristic as gate bias increases. HEMTs with short gate length have drain currents saturate more readily as compared to long gate length. In this paper, the relationship between drain currents saturation and gate bias was analyzed by using a simple series resistance model and was also validated by two-dimensional device simulation. The effects of these saturated transfer characteristics on electron mobility extraction of GaN HEMT were evaluated. Furthermore, the possible extension of GaN HEMT to logic inverter by utilizing the feature of saturation was also discussed.

A Promising New n++-GaN/InAlN/GaN HEMT Concept for High-Frequency Applications

We study enhancement-mode n++-GaN/InAlN/GaN high electron mobility transistors (EHEMTs) by means of two-dimensional numerical device simulation. An introduction of a highly-doped GaN cap layer, which is recessed under the gate, was initially proposed for an improvement of the device performance by diminishing surface traps-related parasitic effects. Our new simulation results reveal that, unlikely to planar transistor structures, the extension of the gate depletion region with drain bias is kept restricted in the presence of a n++-GaN cap layer. This highly-scaled new device concept is very promising for ultra-high frequency performance.

Development of SiC Super-Junction (SJ) Device by Deep Trench-Filling Epitaxial Growth

We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.

Simulation and Optimization of 4H-SiC DMOSFET Power Transistors

Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.

SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits

Abstract Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high- K dielectric HfO 2 as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO 2 considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices.

Integrated tandem dye solar cells

Tandem cells (or multi-junction cells) have been shown to be the most efficient architecture to achieve record performance for most photovoltaic technologies. In fact, tandem architectures allow devices to significantly broaden their overall absorbance spectra providing higher conversion efficiencies compared to individual cells. However, up to now, this has not been true for DSCs where record performances have been always obtained with single cells. This is mainly due to the difficulty of realizing integrated tandem DSC configurations where interlayer losses are minimized. Thus, we propose a new tandem architecture that overcomes the limitation presented so far by tandem DSCs, reporting an efficiency of 6.66% with wide room for improvement. Experimental results are corroborated with two-dimensional device simulations which allow us to understand the working mechanisms and to define optimization routes for this novel architecture. This work opens the way for further optimization of DSC technology, well beyond the actual limits, and also discloses ideas for new possible structures in the related fields of TiO2 tandem catalysts which are important for the realization of solar fuels and electrolyte based devices.

Influence of Surface Recombination on the Performance of SiNW Solar Cells and the Preparation of a Passivation Film

ABSTRACTAl2O3 was deposited on silicon nanowire (SiNW) arrays by atomic layer deposition (ALD) as a passivation layer to reduce surface recombination velocity. As a result, effective minority carrier lifetime was improved from 1.82 to 26.2 μs. From this result, the relative low-surface recombination rate of 2.73 cm/s was obtained from a calculation using one-dimensional device simulation (PC1D). The performance of SiNW solar cells was also simulated by considering the surface recombination velocity on the side of SiNWs using two-dimensional device simulation. It was found that Al2O3 deposited by ALD can improve open-circuit voltage of SiNW solar cells even if the structure has a high-aspect ratio and large surface area. Therefore, improvement in the performance of SiNW solar cells can be expected.

2D modelling of polycrystalline silicon thin film solar cells

The influence of grain boundary (GB) properties on device parameters of polycrystalline silicon (poly-Si) thin film solar cells is investigated by two-dimensional device simulation. A realistic poly-Si thin film model cell composed of antireflection layer, (n + )-type emitter, thick p -type absorber, and (p + )-type back surface field was created. The absorber consists of a low-defect crystalline Si grain with an adjacent highly defective grain boundary layer. The performances of a reference cell without GB, one with n -type and one with p -type GB, respectively, are compared. The doping concentration and defect density at the GB are varied. It is shown that the impact of the grain boundary on the poly-Si cell is twofold: a local potential barrier is created at the GB, and a part of the photogenerated current flows within the GB. Regarding the cell performance, a highly doped n -type GB is less critical in terms of the cell’s short circuit current than a highly doped p -type GB, but more detrimental in terms of the cell’s open circuit voltage and fill factor.

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

Modeling of top and bottom contact structure organic field effect transistors

This research paper proposes analytical models for top and bottom contact organic field effect transistors by considering the overlapping of source-drain (S/D) contacts on to the organic semiconductor layer and effective channel between the contacts. The contact effect is investigated in the proposed models and further verified through two-dimensional (2-D) numerical device simulation. The electrical characteristics are obtained from the linear to saturation regime and analytical outcomes are compared with the simulation and experimental results, which shows good agreement and thus validate the models. The extracted mobilities for top and bottom contact structure include 0.129 and 0.0019 cm2/Vs, and the device resistance as 2.25 and 450MΩ and the contact resistance as 2.25 and 450 MΩ μm2, respectively. The performance difference between top and bottom contact is attributed to the structural difference and morphological disorders of pentacene film around the contacts in bottom contact device which results in higher contact resistance and lower mobility as compared to the top contact device.

A model for avalanche breakdown calculation in low-voltage trench power MOSFET devices

In this work, the avalanche breakdown phenomenon in low-voltage trench power MOSFET is investigated through two-dimensional device simulations. The breakdown dependence from device geometrical characteristics is carefully characterized with particular attention to trench depth and drain region length and doping. An analytical model for breakdown calculation in a trench structure is presented. The analytical model is based on a well-known p+–n unilateral junction model, with a maximum electric field value correction to take into account the trench structure perturbation. It shows good results for a wide range of drift region characteristics and trench lengths.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO2/Si stacked structure on the metal—oxide—semiconductor field-effect transistor (MOSFET) are investigated. The flat-band voltage is revised by considering the influences of stacked structure and metal—semiconductor work function fluctuation. The two-dimensional Poisson's equation of potential distribution is presented. A threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs is developed by solving these Poisson's equations using the boundary conditions. The model is verified by a two-dimensional device simulator, which provides the basic design guidance for metal-gate/high-k/SiO2/Si stacked MOSFETs.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

PMOSFET Performance Enhancement With Strained $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}$ Channels

The inversion-layer hole mobility in MOSFETs with thin silicon-germanium (Si1-xGex) channels grown pseudomorphically on Si is calculated using a self-consistent 6 × 6 k ·p Poisson-Schrodinger mobility simulator calibrated to experimental and simulation data. The addition of uniaxial compressive stress to the inherent biaxial compressive strain of the pseudomorphic Si1-xGex layer is found to further enhance hole mobility by up to 2.5×. Two-dimensional device simulations are used to assess the benefit of the Si1-xGex heterostructure channel for boosting the ON-state current (Ion) of p-channel MOSFETs with a gate length (Lg) of 18 nm; the results show a moderate (10%-40%) improvement over a bulk-Si MOSFET.

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal–oxide–semiconductor (CMOS) process. A novel direct current current–voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum Isub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Optimization of nLDMOS Ruggedness under Unclamped Inductive Switching (UIS) Stress Conditions by Poly-Gate Extension

In this paper, the effect of poly-gate extension on improved ruggedness of n-type LDMOS is evaluated by two-dimensional (2D) device and circuit simulation. Multi-finger dimension of n-type LDMOS is subjected to Unclamped Inductive Switching (UIS) stress test to determine its ruggedness. It is shown that the poly-gate extended device yields approximately 15% higher avalanche energy handling capability (Emax) as compared to that without extended poly-gate region. This work suggests that the improvement in ruggedness of the optimized design is attributed to the suppression and shift of the electric field peaks away from the critical regions. The results from simulation are found to be in good correlation with experimental UIS test results in terms of avalanche energy range, identification of the mechanism of device-failure and hot-spot location. It is believed from the results obtained that this approach will have remarkable impact in the ruggedness if implemented for large-array devices (LAD).

A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect

In this paper, we propose a unique feature exhibited by novel nanoscale metal oxide semiconductor field effect transistors (MOSFETs) with an undoped buried region (UBR) under the channel and a buried oxide only under the source and drain region. The key idea in this work is suppression of the self-heating effect and gate–substrate capacitance improvement by modifying the buried layer. As a result, we demonstrate that the proposed structure called undoped buried region MOSFET (UBR-MOSFET) exhibits gate–substrate improvement in addition to excellent temperature performance when compared to conventional structures. Using two-dimensional and two-carrier device simulation, we have examined various design issues of the UBR-MOSFET and provided the reasons for the improved performance. The simulated results show that the novel structure is a suitable device for high temperature and electrical performances.

Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the SiO2/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

Modeling of silicon nanocrystals based down-shifter for enhanced silicon solar cell performance

A transfer matrix model of a luminescent down-shifter (LDS) layer, consisting of silicon nanocrystals (Si-NCs) embedded in a silicon oxide matrix, on a silicon solar cells is presented. To enhance the efficiency of the silicon solar cell, we propose using a SiO2/Si-NCs double layer stack, as an anti-reflection-coating (ARC) and as a LDS material. The optical characteristics of this stack have been simulated and optimized as a front surface coating. The cell performances have been simulated by means of a two-dimensional device simulator and compared with the performances of a reference silicon solar cell. We found a 6% relative enhancement of the energy conversion efficiency with respect to the reference cell. We demonstrate that this enhancement results from the lower reflectance and from the down-shifter effect of the Si-NCs activated coating stack.

Source/Drain Engineering for High Performance Vertical MOSFET

In this paper, Source/Drain (S/i>/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/i>/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750µA/µm at σS/D =2nm/dec. and σLDD=3nm/dec. when the silicon pillar diameter (D) is 30nm and the gate length (Lg) is 60nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg =60nm and Lg =45nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg =100nm and Lg =60nm because channel length becomes shorter. On the other hand, in the case of Lg =45nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30nm to 10nm, while SS is improved and approaches the ideal value of 60mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.