Twiddle Factors Research Articles

Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

Design of Optimized Radix-4 FFT Processor with Multiplier Sharing Method

To implement the parallel pipelined FFT architecture in OFDM applications. The OFDM has developed in wide band Digital communication. The radix4 algorithm can achieve to reduce the half computational steps compare than the radix2 algorithm and R4MDC is reduces the slices and power consumption than the single path delay feedback. It can be converted into real and imaginary values. To reduce the twiddle factor complexity by using the bit parallel multiplier. It can be exploits the constant twiddle factor when the twiddle factor multiplicatier relocate the twiddle factor multiplications in timing process. The changes can be appeared in multiplications so have to perform the TF at clock signals in two ways data path.

Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R22FFT Processor Using CCSSI Method

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

Using the complement of the cosine to compute trigonometric functions

The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors to general purpose floating-point units. Even in the latter case, the required functionality can be reduced to computing the sine and/or cosine of multiples of a constant angle. The latency of a sine/cosine generator can be reduced by using look-up tables. However, a direct implementation with look-up tables may be unfeasible if the input space is huge. In such a case, look-up tables with a number of entries lower than the size of the input space can be used indirectly. In previously published methods, the reduction in the number of table entries is obtained at the expense of increasing the table width and the computational cost. This paper introduces an alternative technique that makes it possible to reduce the size of the look-up tables as well as the required multiplications. The proposed technique can be used to implement sine/cosine generators of huge input space. It has been used to implement several twiddle factor generators in reconfigurable hardware and has enabled the number of look-up tables to be reduced by between 6 and 26% with respect to previous table-based techniques. Also, these implementations are about 50% faster than those based on Volder’s algorithm.

An Optimized Approach to Generate Multicarrier Radar Signal Using Computationally Efficient Algorithm

MCPC radar signal accedes the property of orthogonal frequency division multiplexing. A term in the complex envelope expression for MCPC shows similarity to the twiddle factor which paved a way for generating MCPC signal by incorporating computationally efficient algorithm which produces envelope as similar with conventional method along with the reduction in the number of computations. Various transforms were validated, among all of them FFT implementation results gave rise to the least PMEPR which is the most essential for using power amplifiers in the faithful manner.

Accelerating number theoretic transform in GPU platform for fully homomorphic encryption

In scientific computing and cryptography, there are many applications that involve large integer multiplication, which is a time-consuming operation. To reduce the computational complexity, number theoretic transform is widely used, wherein the multiplication can be performed in the frequency domain with reduced complexity. However, the speed performance of large integer multiplication is still not satisfactory if the operand size is very large (e.g., more than 100K-bit). In view of that, several researchers had proposed to accelerate the implementation of number theoretic transform using massively parallel GPU architecture. In this paper, we proposed several techniques to improve the performance of number theoretic transform implementation, which is faster than the state-of-the-art work by Dai et al. The proposed techniques include register-based twiddle factors storage and multi-stream asynchronous computation, which leverage on the features offered in new GPU architectures. The proposed number theoretic transform implementation was applied to CMNT fully homomorphic encryption scheme proposed by Coron et al. With the proposed implementation technique, homomorphic multiplications in CMNT take 0.27 ms on GTX1070 desktop GPU and 7.49 ms in Jetson TX1 embedded system, respectively. This shows that the proposed implementation is suitable for practical applications in server environment as well as embedded system.

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

A Low-SWaP 16-Beam 2.4 GHz Digital Phased Array Receiver Using DFT Approximation

A low-complexity approximation for the 16-point DFT and its respective multiplierless fast algorithm is proposed. A receive mode multibeam phased-array experiment was realized at 2.4 GHz employing a 16-element IQ receiver array that uses the proposed approximate spatial DFT in real-time in order to achieve multibeam digital beamforming. The 16-beam digital receiver experiment uses a ROACH-2 based Xilinx Virtex-6 FPGA platform for both digital beam computation as well as to perform the multireceiver analog-to-digital conversion. Receive mode RF beams were measured and compared to the exact DFT (realized with fixed-point multipliers with 8-bit twiddle factors). The measured approximate DFT closely followed the measured beams resulting from the fixed-point conventional DFT implementation. The approximate DFT achieves RF beam performance (mainlobe gain, sidelobes) similar to the DFT at the cost of a small error which would be tolerable for the majority of multibeam phased-array receivers. The 16-point approximate DFT provides a hardware reduction of $\sim$70% with respect to FFTs, setting up a low size, weight and power (SWaP) system.The maximum magnitude error of the filter bank response is 0.106 ($\approx -20$ dB).

FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm

The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

Selecting FFT Word Length for an OFDM Receiver That Supports Undersampling

In this paper, we focus on Orthogonal Frequency Division Multiplexing (OFDM) transceivers where undersampling is employed by the receiver Analog/Digital Converter (ADC) when sparse information is exchanged. Several Fast Fourier Transform (FFT) symmetry properties are exploited to allow the substitution of specific input values by others that have already been sampled by the ADC. Several architectures have been proposed in the literature for efficient FFT implementations in terms of power, speed and hardware resources. The FFT input/output values, twiddle factors, etc., are complex numbers with their real and imaginary parts being represented using fixed point format. A tradeoff has to be made between rounding error and complexity. The optimal minimum FFT word length is investigated by combining the undersampling and the rounding error. A configurable new FFT architecture has been developed in hardware description language to test the error model with various FFT sizes, word lengths and Quadrature Amplitude Modulations (QAM). A system designer can take into account the sparseness of the input data and define the desired rounding and undersampling error relation. Τhe developed error model would then predict the required word length and ADC resolution with average Root Mean Square Error (RMSE) less than 1.

A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC.

Low Complexity FFT Factorization for CS Reconstruction

In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.

Long-Time Coherent Integration for Frequency Hopping Pulse Signal via Phase Compensation

Long time coherent integration technique is one of the most important methods to improve the radar detection ability of a weak maneuvering target. However, the integration performance may be greatly influenced by the range migration and Doppler migration effects caused by the complex motions of maneuvering targets when long time integration is applied. Besides, the frequency hopping characteristic of the transmitted signal will also result in Doppler migration which cannot be eliminated by the conventional coherent integration method. To deal with this problem, a novel coherent integration method based on phase compensation is proposed. By using the frequency hopping pattern, the Doppler migration is eliminated by adding an extra phase in the twiddle factor of Fourier Transform in this proposed method. Since the phase error is compensated, long time coherent integration can be achieved. The effectiveness of the proposed method is verified by the simulation results and the performance analysis.

Research on FFT Algorithm Use SMP System

Based on the theoretical research of a series of algorithms of adaptive beamforming and space-time adaptive processing, it is necessary to discuss the implementation of related algorithms on the machine hardware platform. Fast Fourier transform (FFT) is an essential process in this implementation. With the development of array antennas, the number of points to be calculated by the FFT has also increased significantly. Therefore, the ultra-large point FFT has become a key technology for current antenna signal processing. Most of the existing FFT algorithms are researched based on single-core processors, and there is very little literature on the research of super-large-point FFT algorithms suitable for Symmetric Multiprocessor (SMP). In this paper, through analyzing the characteristics of a symmetric multi-processor (SMP) parallel processing system, the very large FFT fast algorithm (VLFFT) is proposed. This algorithm significantly reduces the dependence on memory and improves the FFT's performance using the limited rules of the one-dimensional sequence split, changing the twiddle factor calculation method, and optimizing the data distribution and storage access. And the research's optimized very large FFT algorithms is also summarized in the paper. Experiment results show that the algorithm is suitable for the SMP platform and can effectively solve the problem of the very large FFT, which make single-core processors harder to realize.

A Design of Input-Decimation Technique for Recursive DFT/IDFT Algorithm

In this paper, an input-decimation technique for the recursive discrete Fourier transform (RDFT)/inverse DFT (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is worth noting that the input-decimation approach is presented to decrease the number of input sequences for the recursive filter so that the computation cycle of RDFT/RIDFT can be shortened to meet the computing time requirement ( $3.6~{\mu }s$ ) for the high-speed broadband communication systems. Therefore, the input-decimation RDFT/RIDFT algorithm is able to carry out at least 55.5% reduction of the total computation cycles compared with the considered algorithms. Furthermore, holding the advantages of input-decimation technique, the computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. The area and the power consumption can be minimized by employing the cost-efficient constant multiplier with the refined signed-digit expression of twiddle factors. Finally, the physical implementation results show that the core area is $0.37\times 0.37$ mm2 with $0.18~\mu \text{m}$ CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of computational efficiency per unit area (CEUA) and really outperform the previous works.

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias

In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the proposed TF is developed based on the adaptive method of the coordinate rotation digital computer (CORDIC) algorithm. The 65-nm SOTB technology was chosen because of its ultra-low-power advantage. Furthermore, the back-gate bias technique can be applied on an SOTB chip to adjust the operation for high-performance or low-power requirement. The layout of the SOTB 65-nm TF core is about 22869 gate-count on the die area of 86721 $ \mu \text {m}^{2}$ . The measurement results show that the core reached its highest operating frequency of 55 MHz at the 1.2-V supply voltage (VDD) with the forward back-gate bias (FBB) ≥ 1.5 V. The power and energy consumptions at this point were 1.54 mW and 27.91 pJ/cycle, respectively. The lowest operating VDD was at 0.5 V with the FBB ≥ 0.5 V. In the standby mode, when the clock-gating technique was deployed, the leakage current can be reduced to 0.4 nA at the 0.4 V VDD and −2.5-V reverse back-gate bias (RBB).

DFT processor implementation scheme based on Rader algorithm

The implementation of a discrete Fourier transform (DFT) algorithm plays a key role in many real-time applications. This study mainly deals with the design and implementation of a DFT processor with non-power-of-two (prime) problem sizes using the Rader algorithm. The proposed design focuses on increasing the speed to fulfil the requirements of the real-time data transmission by enabling data rates up to 10 Gbps. Despite its limitation to the prime size, it remains a promising tool in the signal processing aspect and takes its place among other techniques to achieve high-speed wireless communication. By avoiding the cumbersome process during twiddle factors computation as well as the butterfly structure, the outcome preludes to an ambitious architecture dedicated to high-speed design reaching over 233 and 92 MHz for DFT lengths of 7 and 67, respectively, on Virtex 6. Thereby, the obtained results prove the efficiency of the algorithm and show the trade-off to be established in terms of occupied area, throughput, latency, and power consumption.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs. An optimized conflict-free data access scheme is also proposed to support multiple butterflies at any radices. The processor is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer). The electronic design automation synthesis result based on a 65-nm technology shows that the processor area is 1.46 mm2. The processor supports 972 MS/s 4096-point FFT at 250 MHz with a power consumption of 68.64 mW and a signal-to-quantization-noise ratio of 66.1 dB. The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs.