Twiddle Factors Research Articles

A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.

On a wideband fast fourier transform for a radio telescope

The radio telescope analyzes a radio frequency from celestial objects by using fast Fourier transform (FFT). In this application, its bandwidth f is wider than that of the typical FFT. Since the amount of hardware for the typical FFT circuit is proportional to the bandwidth f, a special technique is necessary for this application. This paper shows a realization of wideband FFT for the radio telescope on an FPGA. We show that the memory size for the conventional FFT, which consists of the twiddle factor memory and the transpose memory, is too large. We replace the twiddle factor memory with the pipelined CORDIC. To reduce the number of transpose memories, we increase the radix of the FFT from 22 to 2k, also we use the DDR2SDRAM to implement the transpose memory. We implement the 230-FFT on an Altera's Stratix IV GX530 FPGA. It performs the 230-FFT operations in 1.5 seconds. Compared with the Altera's FFT library, our FFT circuit realizes 214 times wider bandwidth on the same FPGA. Also, compared with Tesla S1070 utilizing four GPUs, our FFT circuit is faster and dissipates lower power.

Efficient Implementation of Fast Fourier Transform Using NOC

In this paper, improved algorithms for radix-8 FFT are presented. Various schemes have been proposed for computing FFT. It has Different target domains of applications and different tradeoffs between flexibility and performance. Typically, they need reconfigurable array of processing elements .The applications have been restricted to domains based on floating arithmetic. We introduce floating-point Arithmetic which is based on processing elements. After developing the FFT design we present a routing Algorithm and use topology to reduce power dissipation. These modified radix-8 algorithms provide savings of more than 33% in the number of twiddle factor evaluations I. Introduction An Orthogonal frequency division multiplexing (OFDM) signal consists of a sum of subcarriers that are modulated by using Phase Shift Keying (PSK) or Quadrature Amplitude Modulation (QAM). These days, OFDM technique is widely used for high-speed digital communications, such as xDSL, DAB, DVB-T/H, and WLAN. In OFDM system, Discrete Fourier Transform (DFT)/Inverse-DFT are used and it is a very important operation. Since DFT/IDFT computation requires a large amount of arithmetic operations, we need an efficient FFT algorithm which can reduce the number of arithmetic operations to meet real time computation in OFDM systems.

一种新的过零单边干涉图切趾加权函数

A novel apodization function is proposed.The new apodization function multiplied by zero-crossing single sided interferogram can average the product of twiddle factor and intensity of two points having the same optical path difference,and reduce the error due to the data around zero optical path difference used twice.The simulation results show that the new apodization function fits better in some serious unsymmetrical interferograms than the Mertz apodization function and can minish the spectral distortion.Moreover,the computational complexity can be reduced significantly.The new apodization function can be widely applied to zero-crossing single sided interferogram data processing of fourier transform spectrometer.

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

Several SOA (state of the art) self-tuning software libraries exist, such as the Fastest Fourier Transform in the West (FFTW) for fast Fourier transform (FFT). FFT is a highly important kernel and the performance of its software implementations depends on the memory hierarchy's utilization. FFTW minimizes register spills and data cache accesses by finding a schedule that is independent of the number of the registers and of the number of levels and size of the cache, which is a serious drawback. In this paper, a new methodology is presented, achieving improved performance by focusing on memory hierarchy utilization. The proposed methodology has three major advantages. First, the combination of production and consumption of butterflies' results, data reuse, FFT parallelism, symmetries of twiddle factors and also additions by zeros and multiplications by zeros and ones when twiddle factors are zero or one, are fully and simultaneously exploited. Second, the optimal solution is found according to the number of the registers, the data cache sizes, the number of the levels of data cache hierarchy, the main memory page size, the associativity of the data caches and the data cache line sizes, which are also considered simultaneously and not separate. Third, compilation time and source code size are very small compared with FFTW. The proposed methodology achieves performance gain about 40% (speed-up of 1.7) for architectures with small data cache sizes where memory management has a larger effect on performance and 20% (speed-up of 1.25) on average for architectures with large data cache sizes (Pentium) in comparison with FFTW.

A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system

The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Since 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the Winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60×63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized CoOrdinate Rotation DIgital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.

Generating and Searching Families of FFT Algorithms

A fundamental question of longstanding theoretical interest is to prove the lowest exact count of real additions and multiplications required to compute a power-of-two discrete Fourier transform (DFT). For 35 years the split-radix algorithm held the record by requiring just 4n log2 n − 6n + 8 arithmetic operations on real numbers for a size-n DFT, and was widely believed to be the best possible. Recent work by Van Buskirk and Lundy demonstrated improvements to the split-radix operation count by using multiplier coefficients or “twiddle factors” that are not nth roots of unity for a size-n DFT. This paper presents a Boolean Satisfiability-based proof of the lowest operation count for certain classes of DFT algorithms. First, we present a novel way to choose new yet valid twiddle factors for the nodes in flowgraphs generated by common power-of-two fast Fourier transform algorithms, FFTs. With this new technique, we can generate a large family of FFTs realizable by a fixed flowgraph. This solution space of FFTs is cast as a Boolean Satisfiability problem, and a modern Satisfiability Modulo Theory solver is applied to search for FFTs requiring the fewest arithmetic operations. Surprisingly, we find that there are FFTs requiring fewer operations than the split-radix even when all twiddle factors are nth roots of unity.

A COOLEY-TUKEY MODIFIED ALGORITHM IN FAST FOURIER TRANSFORM

We would like to propose a Cooley-Tukey modied algorithm in fast Fourier transform(FFT). Of course, this is a kind of Cooley-Tukey twiddle factor algorithm and we focused on the choice of integers. The proposed algorithm is better than existing ones in speeding up the calculation of the FFT.

Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.

New Parametric Discrete Fourier and Hartley Transforms, and Algorithms for Fast Computation

In this paper, we propose a new reciprocal-orthogonal parametric discrete Fourier transform (DFT) by appropriately replacing some specific twiddle factors in the kernel of the classical DFT by independent parameters that can be chosen arbitrarily from the complex plane. A new class of parametric unitary transforms can be obtained from the proposed transform by choosing all its independent parameters from the unit circle. One of the special cases of this class is then exploited for developing a new one-parameter involutory discrete Hartley transform (DHT). The proposed parametric DFT and DHT can be computed using the existing fast algorithms of the DFT and DHT, respectively, with computational complexities similar to those of the latter. Indeed, for some special cases, the proposed transforms require less number of operations. In view of the fact that the transforms of small sizes are used in some image and video compression techniques and employed as building blocks for larger size transform algorithms, we develop new algorithms for the proposed small-size transforms. The proposed parametric DFT and DHT, in view of the introduction of the independent parameters, offer more flexibility in achieving better performance compared to the classical DFT and DHT. As examples of possible applications of the proposed transforms, image compression, Wiener filtering, and spectral analysis are considered.

A low-power 64-point pipeline FFT/IFFT processor for OFDM applications

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs

In this work we consider optimized twiddle factor multipliers based on shift-and-add-multiplication. We propose a low-complexity structure for twiddle factors with a resolution of 32 points. Furthermore, we propose a slightly modified version of a previously reported multiplier for a resolution of 16 points with lower round-off noise. For completeness we also include results on optimal coefficients for eight-points resolution. We perform finite word length analysis for both coefficients and round-off errors and derive optimized coefficients with minimum complexity for varying requirements.

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.

Accurate, Guaranteed Stable, Sliding Discrete Fourier Transform [DSP Tips &amp; Tricks

This article presented a novel method of computing the SDFT that we call the modulated SDFT (mSDFT). The sliding discrete Fourier transform (SDFT) is a recursive algorithm that computes a DFT on a sample-by-sample basis. The accumulated errors and potential instabilities inherent in traditional SDFT algorithms are drastically reduced in the mSDFT. We removed the twiddle factor from the feedback in a traditional SDFT resonator and thus the finite precision of its representation is no longer a problem.

Low-Computation-Cycle, Power-Efficient, and Reconfigurable Design of Recursive DFT for Portable Digital Radio Mondiale Receiver

Low-cost, fast-computational, power-efficient, and reconfigurable design for recursive discrete Fourier transform (RDFT) is proposed in this brief. The proposed method is the first integration that collated both the prime factor algorithm (PFA) and the Chinese reminder theorem (CRT) into a recursive algorithm. Hence, a multicycle RDFT algorithm (PFA + CRT + RDFT) and its hardware implementation are produced and presented here in great detail. Compared with some well-known recursive algorithms, the significant improvements for the proposed algorithm can be summarized as follows: 1) The number of computational cycles of the proposed algorithm can be saved by up to 88.5%; 2) The number of multiplications and additions for the proposed algorithm is dramatically reduced by up to 85.2% and 85.2%, respectively; 3) The amount of coefficient read-only memory for storing the twiddle factors totally takes 694 words fewer than those of other existing RDFT algorithms; 4) The hardware cost of the proposed algorithm only takes four real multipliers and eight real adders. This design is more suitable for digital radio mondiale (DRM) systems, such as coded orthogonal frequency-division-multiplexing modulation. The proposed RDFT algorithm was designed and fabricated using a 0.18-μm 1P6M CMOS process. The core area is 521 × 508 μm2, and this hardware accelerator only consumes 8.44 mW at 25 MHz. Furthermore, the performance index of power for this design is three times discrete Fourier transform (DFT) per energy of previous work. Additionally, it can calculate the 288/256/176/112-point DFTs for a portable DRM receiver.

Implementación en Sistemas Embebidos de la Transformada Discreta de Hartley

Las transformaciones ortogonales han sido de gran utilidad en la caracterización y procesamiento de señales. En particular la Transformada de Hartley permite obtener representaciones tiempo-frecuencia y viceversa. En este trabajo se presenta un algoritmo para el cálculo de la Transformada Discreta de Hartley en sistemas embebidos con el objetivo de minimizar la carga computacional y la capacidad de almacenamiento necesaria. Se aprovecha la similitud con la Transformada Discreta de Fourier para usar un algoritmo de cálculo rápido y se reduce el número de funciones trigonométricas calculadas usando los factores de giro (twiddle factors). En general la implementación permite aumentar el tamaño de la ventana de transformación y aumentar la velocidad de cálculo respecto al cálculo directo.

Improved Twiddle Access for Fast Fourier Transforms

Optimizing the number of arithmetic operations required in fast Fourier transform (FFT) algorithms has been the focus of extensive research, but memory management is of comparable importance on modern processors. In this article, we investigate two known FFT algorithms, G and GT , that are similar to Cooley-Tukey decimation-in-time and decimation-in-frequency FFT algorithms but that give an asymptotic reduction in the number of twiddle factor loads required for depth-first recursions. The algorithms also allow for aggressive vectorization (even for non-power-of-2 orders) and easier optimization of trivial twiddle factor multiplies. We benchmark G and GT implementations with comparable Cooley-Tukey implementations on commodity hardware. In a comparison designed to isolate the effect of twiddle factor access optimization, these benchmarks show typical speedups ranging from 10% to 65%, depending on transform order, precision, and vectorization. A more heavily optimized implementation of GT yields substantial performance improvements over the widely used code FFTW for many transform orders. The twiddle factor access optimization technique can be generalized to other common FFT algorithms, including real-data FFTs, split-radix FFTs, and multidimensional FFTs.

16-Point Reversible Integer Discrete Fourier Transform With 12 Control Bits

This correspondence discusses the reversible integer 16-point discrete Fourier transform (RiDFT) which uses integer operations with control bits. The decomposition of the RiDFT is based on the paired representation, when the Fourier transform is split recursively into a set of short transforms of orders 8, 4, 2, and 1. Control bits allow for inverting the integer approximations of multiplications by twiddle factors. The proposed 16-point RiDFT uses 16 operations of real multiplication and 62 additions. The integer approximation of the transform with eight control bits with additional two lifting schemes, which requires two more multiplications, is also considered.

PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

Hardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband Applications

Problem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 M sample sec-1. Therefore, it is a challenge to realize the physical layer especially the components with high computational complexity in Very Large Scale Integration (VLSI) implementation. Fast Fourier Transform (FFT) block which plays an important role in MB-OFDM system is one of these components. Furthermore, the execution time of this module is only 312.5 ns. Therefore, if employing the traditional approach, high power consumption and hardware cost of the processor will be needed to meet the strict specifications of the UWB system. The objective of this study was to design an Application Specific Integrated Circuit (ASIC) FFT processor for this system. The specification was defined from the system analysis and literature research. Approach: Based on the algorithm and architecture analysis, a novel Genetic Algorithm (GA) based Canonical Signed Digit (CSD) Multiplier less 128-point FFT processor and its inverse (IFFT) for MB-OFDM UWB systems had been proposed. The proposed pipelined architecture was based on the modified Radix-22 algorithm that had same number of multipliers as that of the conventional Radix-22. However, the multiplication complexity and the ROM memory needed for storing twiddle factors coefficients could be eliminated by replacing the conventional complex multipliers with a newly proposed GA optimized CSD constant multipliers. The design had been coded in Verilog HDL and targeted Xilinx Virtex-II FPGA series. It was fully implemented and tested on real hardware using Virtex-II FG456 prototype board and logic analyzer. Results: From the synthesis reports, the proposed GA optimized CSD constant complex multiplier achieved 79 and 50% equivalent gates and latency efficiency when compared to the conventional complex multiplier. Conclusion: As a conclusion, we successfully implemented 128-points FFT/IFFT processor with the proposed architecture that can meet the requirement of MB-OFDM UWB system with higher throughput and less area compared to conventional architecture.