Low Complexity FFT Factorization for CS Reconstruction

Alahari Radhika,Research Scholar, Department Of Ece, Jnt University, Kakinada, Ap, India ,K Kishan Rao, ,K Satya Prasad

doi:10.35940/ijeat.c4675.029320

Alahari Radhika, Research Scholar, Department Of Ece, Jnt University, Kakinada, Ap, India + Show 3 more

Open Access

https://doi.org/10.35940/ijeat.c4675.029320

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Abstract

In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.

Highlights

In recent years high speed and improved end quality results are emerged as important aspects of many digital systems like Clinical imaging [1], wireless communication [2] and IoT Applications [3] which give rise to both bandwidth and frequency
Verilog HDL is used to model the proposed architecture and FPGA synthesizer with cyclone-II family devices is used for the state-of-the-art comparison
In this brief ultimate goal is to attain high performance and hardware complexity reduction with less resource utilization which is validated from the FPGA QUARTUS II EDA synthesis results

Summary

Introduction

In recent years high speed and improved end quality results are emerged as important aspects of many digital systems like Clinical imaging [1], wireless communication [2] and IoT Applications [3] which give rise to both bandwidth and frequency. Owing to the inclusion of wideband and high throughput signal processing, this conventional method requires a high sampling rate, which tends to energy consumption problems. * Correspondence Author results quality which is referred to as Compressive Sampling (CS). In this method signals are acquired with some measured value and utilize some unique algorithm at the receiver side to restore the input signal from the down rated measured values. It has advantage of least possible samples requirement for accurate reconstruction of input signal which is far less as compared to its counterpart sampling theory

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