Tunnel Oxide Research Articles

String-level compact modeling for dynamic operation and transient analysis of 3D charge trapping flash memory

In this article, we propose a string-level compact model, which is based on accurate and seamless channel electrostatic potential, for dynamic operation of 3D charge trapping flash (CTF) memory. First, we introduce a unit cell model for 3D CTF memory structure based on a conventional BSIM-CMG model using an extended netlist of equivalent circuits which describe the gate-all-around (GAA) structure composed of a metal gate, a blocking oxide, a charge trapping layer, and a tunneling oxide. Then, a string-level compact model is proposed, implying three advantages of inter-cell behaviors, seamless channel potential and process variation. To enhance the accuracy of the model behavior, extended model parameters are extracted showing good agreement with experimental data, such as I-V characteristics, program/erase speed, and incremental step pulse programming (ISPP). Furthermore, to predict channel electrostatic potential more precisely, we verify simulation program with integrated circuit emphasis (SPICE) simulation results of positively and negatively boosted channels comparing them with technology computer-aided design (TCAD) simulation results. Finally, we demonstrate that the proposed model can be efficiently applied to circuit simulation for analysis of the disturbance or failure mechanism and would equip the circuit designers and system architects with an effective tool for design optimization of 3D CTF memory devices.

A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor☆

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Floating-gate MOS transistor, which has extraordinary performances. The MOS has a large timing window of 4 V, a high gate capacitance ratio parameter of 0.645, and a high Write/Erase speed of 50 ms/70 ms. Interestingly, the results are obtained with a thin thickness of 9 nm of a tunnel oxide layer which is smaller than such layer in other works and low supply voltages in which the control gate, drain, and source voltage values are ± 6 V, 1 V, and 1 V, respectively. In addition, our paper presents the effect of the control gate voltage on the performance of the device when it increases from 6 V to 18 V.

Optimization of activated phosphorus concentration in recrystallized polysilicon layers for the n-TOPCon solar cell application

The pivotal structure of n-TOPCon (tunnel oxide passivating contact) solar cells is the passivating contact structure composed of a heavily doped polysilicon (poly-Si) layer and an ultrathin silicon oxide (SiOx), which can provide excellent selectively carrier transport. The activated phosphorus concentration in the passivating contact structure plays a crucial role in the passivation quality and contact resistivity performance. By adjusting PH3 flow rate, SiOx thickness and activation temperature, three different activated phosphorus concentrations in poly-Si were achieved in this work, the phosphorus concentration from SiOx to silicon bulk decreased at the same rate. It can be found that the passivation quality decreases with increasing concentration and the contact resistivity decreases significantly. With the aid of ellipsometry, we successfully extracted the refractive index n and extinction coefficient k of three poly-Si with different activated phosphorus concentrations. The extracted n and k values can well feedback the influence of concentration change on short-circuit current density in the simulation. Due to the high concentration led to the decrease of the open circuit voltage and short circuit current of the final TOPCon solar cell, but the obvious filling factor benefit can be obtained, only moderate doping concentration can obtain the best efficiency performance. Finally, the activated phosphorus concentration of about 3 × 1020 cm−1 can obtain the best efficiency, >24.8% on average.

Effects of Geometry and Cycling on the Radiation Response of Charge-Trapping NAND Memory Devices With SiON Tunneling Oxide

The effects of geometry and cycling are evaluated for charge-trapping NAND memory devices with SiON tunneling layers. Processing splits include SiON tunneling layers with and without H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> high-pressure annealing. Programmed and erased devices were irradiated up to 500 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with 10-keV X-rays. Excellent retention and endurance are demonstrated for these devices before and after irradiation. Scaling devices to smaller dimensions enhances program/erase efficiency and radiation tolerance.

Non-volatile charge-trap memory characteristics with low-temperature atomic layer deposited HfO2−x charge-trap layer and interfacial tunneling oxide formed by UV/ozone treatment

Non-volatile charge-trap memory characteristics were investigated in the thin-film transistors with an indium-gallium-zinc oxide channel and an oxygen-deficient hafnium oxide (HfO2−x) charge-trap layer deposited by atomic layer deposition (ALD). The HfO2−x charge-trap layer was subsequently UV/ozone treated to convert its surface to more insulating tunneling oxide. The HfO2−x charge-trap layer deposited at a low temperature of 50 °C was found to have a high defect density to store electrons with an areal density of 1.57 × 1012 cm−2 calculated from the threshold voltage (VT) shift of 30 V. The VT shifted positively as a result of electron charging in the charge-trap layer by applying positive gate bias, and then reduced back reversibly by applying negative bias. Also, the shifted VT is retained over time, rendering non-volatile memory characteristics. The improved reliability of charge storage is expected to come from eliminating trap states at the interface by UV/ozone treatment. It also simplifies the overall fabrication process by removing additional processing steps of tunneling oxide layer deposition. The proposed device turned out to have a large memory window thanks to the high trap density in the HfO2−x charge-trap layer deposited by low-temperature ALD and the good non-volatility by using UV/ozone treatment.

A Review on p-Type Tunnel Oxide Passivated Contact (TOPCon) Solar Cell

A Review on p-Type Tunnel Oxide Passivated Contact (TOPCon) Solar Cell

Bi-polysilicon passivating contact technique for crystalline silicon solar cell

Polysilicon (poly-Si) passivating contacts overcome the direct metal–semiconductor contact drawback of traditional industrial crystalline silicon (c-Si) solar cells by inserting a layer stack of poly-Si and silicon oxide layers at the rear full-area metal/c-Si interface, which is well-known as a tunnel oxide passivating contact (TOPCon). In conventional industrial TOPCon devices, the direct contact problem affects the emitter, which deteriorates the passivation quality and suppresses the open-circuit voltage (Voc). We herein introduce an innovative bi-poly-Si technique (Bi-TOPCon) featuring rear full-area passivated poly-Si and emitter locally passivated poly-Si to improve the passivation quality of the TOPCon device. The local emitter poly-Si is introduced using metal mask alignment, and its properties are optimised toward high passivation quality and low contact resistance. The Bi-TOPCon device shows a significant improvement in Voc (Voc > 700 mV). Bi-TOPCon is a promising technology for high-efficiency, next-generation industrial TOPCon devices.

Improvement in the Performance of P-Type Tunnel Oxide Passivated Contact Solar Cell With Selective Tunneling Junctions Underneath the Contacts on Front Side

Industrial silicon solar cells are now moving further from passivated emitter and rear contact (PERC) toward Tunnel Oxide Passivated contact (TOPCon) technology. The efficiency of the PERC solar cell is improved by TOPCon technology, in which the rear side is fully passivated by an oxide/poly-Si tunneling junction. The performance of a TOPCon solar cell may further be improved by the incorporation of selective tunneling junctions underneath the front contacts. Some fabrications have been reported on a similar structure for an n-type Si substrate but they have not achieved the expected results. Also, a detailed study has not been done yet. Using 3-D sentaurus technology computer aided design (TCAD) simulation software, a detailed analysis has been done on the modified structure through the optimization of the tunnel oxides, the interfaces, the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> poly-Si layer, the selective (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> -poly-Si) tunneling junctions underneath the front contacts, etc., which has not been done earlier. It is seen that a thick n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> poly-Si layer causes parasitic absorption of light, whereas a very thin poly-Si layer cannot provide sufficient field for tunneling of carriers. A thicker tunnel oxide produces a high series resistance, whereas a very thin tunnel oxide cannot restrict the minority carriers to reach to the contacts. Therefore, an optimization is required and the optimization is done based on a fabricated bifacial p-TOPCon solar cell reported in the literature with an efficiency of 21.2% and bulk lifetime of 200 μs. After performing all the modifications in the fabricated reference cell and optimizing different parameters, the efficiency is improved by 3.5% in absolute. The efficiency is further improved to 25.4% with the bulk lifetime of 1 ms.

Study of hydrogenation with electron injection for TOPCon solar cells with different tunneling oxide layers

In order to further improve the photovoltaic conversion efficiency of tunnel oxide passivated contact (TOPCon) solar cells, the hydrogenation with electron injection (HEI) technique on TOPCon solar cells with different processes for preparing tunneling SiOx layers was investigated. The experimental results showed that the conversion efficiency enhancement of TOPCon solar cells with a tunneling SiOx layer prepared by a N2O plasma oxidation method (PO method) was lower than that of the cells prepared by an indirect thermal oxidation method (TO method) under the same HEI treatment conditions. Further studies proved that the improvement effect after HEI treatment was closely related to the denseness of the tunneling SiOx layer: HEI treatment for TOPCon solar cells with a low dense tunneling SiOx layer (TO method) requires higher temperature, higher current, and longer time to achieve a better improvement, while the HEI parameters of cells with a high dense tunneling oxide layer (PO method) need to be readjusted. By optimizing the HEI parameters for cells prepared by the PO method, the power conversion efficiency (PCE) of the cells was finally improved by 0.098%abs. The PCE was improved from the original negative growth to a level close to that of the TOPCon cells prepared by the TO method. This result provided an improved process flow to further increase the efficiency of TOPCon solar cells.

Simulation and optimization of polysilicon thin film deposition in a 3000 mm tubular LPCVD reactor

The high photoelectric conversion efficiency of tunnel oxide passivating contacts (TOPCon) photovoltaic (PV) cells and their process compatibility are increasingly recognized by the industry, making it of growing importance to develop deposition process technologies for high-capacity polysilicon thin films. Currently, the size of LPCVD reactors for preparing polysilicon thin films in the industry is getting enlarged, which directly leads to the degradation of axial uniformity of polysilicon thin films. In this paper, a coupled multi-physics field model is established to simulate the polysilicon thin-film Low Pressure Chemical Vapor Deposition (LPCVD) process based on COMSOL Multiphysics platform, and the validity of the model is verified by comparing experimental data with simulation results. By investigating the flow field, thermal field, chemical reaction field and surface reaction field, the effects of the process parameters such as chamber temperature and pressure are investigated, as well as characteristics of the polysilicon thin films deposition. The results show that the uniformity of thin films decreases with increasing temperature and pressure, and the deposition rate of thin films increases as temperature and pressure increase. With the help of optimized the process parameters, the deposition rate of polysilicon thin films was increased by 13.0% and the uniformity of thin films was controlled above 96%. The uniformity of the films can be further improved to 96.7% by optimizing the temperature zone parameters and adopting the wafers placement strategy.

Simulation, Experimental Evaluation, and Characterization of a Novel Grid Line Design for TOPCon Solar Cells With Reduced Silver Consumption

Silver paste accounts for a substantial portion of the nonsilicon cost of tunnel oxide polysilicon contact solar cells. Silver consumption is as well a major concern for material sustainability of global PV manufacturing. It is necessary to propose innovative grid line designs to reduce the amount of silver paste. Partially interrupting the metal fingers (also known as “Finger Break”) between the bus bars in areas where the fingers carry a relatively small current is a good method for reducing silver consumption in industrial production. Under the assumption of uniform generated current density (ISO-current), this article discusses the impact of the width of finger interruption on the cell efficiency under two different scenarios. Through simulations, experiments, and outdoor testing, it was found that one of the considered novel grid designs can save silver paste to a great extent, but suffers a rapid decline in power conversion efficiency, and also poses potential stability risks, while the other grid design not only saves silver, it does not severely affect the efficiency, and can be used outdoors while maintaining stability. Based on the different light intensities, the finger interruption width can be as high as 5 mm, resulting in a saving of 9.32 mg (∼1.61 mg/W) of silver paste on the front surface of 158.75 cm×158.75 cm solar cell, for a reduction of 12.97% of the original front silver consumption.

TCAD based numerical exploration of industrially feasible tunnel oxide passivated contact on p-type silicon

Tunnel Oxide Passivated Contact (TOPCon) is considered as an immediate successor of Passivated Emitter and Rear Contact (PERC). Rear side full area hole selective passivating contact with front n+ diffused emitter on p-type silicon (Si) (p-TOPCon) would be an incremental upgrade from PERC. However, limited studies are present on p-type Si and most of them are on TOPCon with rear full area electron selective contact (n-TOPCon). In this work, we explore the potential of p-TOPCon by incorporating industry relevant material and process parameters in Sentaurus TCAD simulations. These include bulk lifetime (τb), wafer resistivity (ρ), polysilicon related rear parameters, front emitter sheet resistance (Rsheet) and its passivation (Sfront), and finger width (Wfinger). Simulation results are benchmarked against PERC and n-TOPCon. p-TOPCon outperforms PERC and has lower sensitivity to wider range of τb, ρ, and Sfront. Simulation suggests that an efficiency of 23.83% can be achieved for industrially feasible τb of 5 ms, ρ of 1 Ω-cm, emitter Rsheet of 132 Ω/sq, and Wfinger of 20μm for p-TOPCon. Replacement of diffused emitter with n-TOPCon would be ideal after accomplishing above anticipated advancements and in such a scenario, efficiency > 24.4% can be achieved on p-type Si.

Perovskite/Silicon Tandem Solar Cells: Choice of Bottom Devices and Recombination Layers

Perovskite/silicon tandem solar cells have been intensively studied in recent years, and their efficiencies have rapidly increased owing to the numerous efforts in this field. A question about which type of silicon solar cell is the most suitable subcell in tandem devices emerges. Herein, three attractive silicon solar cells are summarized, including passivated-emitter rear-cell (PERC), tunnel oxide passivated contact (TOPCon), and heterojunction (HJT) cells. Their structures and features are elucidated for a clear understanding of the mechanism and potential of optimum performance. Moreover, the characteristics and performance of perovskite/silicon tandem cells with PERC, TOPCon, and HJT subcells are contrasted and discussed. The significant contribution of the passivation layer and structure design on both sides to photovoltaic properties of tandem devices is emphasized. Especially, the recombination layer between two subcells is analyzed in depth in terms of material chemistry, light absorption, and charge transport with a review on preparing the optimized structure.

Concurrently Preparing Front Emitter and Rear Passivating Contact via Continuous PECVD Deposition Plus One‐Step Annealing for High‐Efficiency Tunnel Oxide Passivating Contact Solar Cells

Although tunnel oxide passivating contact (TOPCon) solar cells (SCs) have achieved great success in the photovoltaic (PV) industry, the ultrahigh temperature to prepare boron emitters prolongs the preparation processes and increases the thermal budget. Herein, a new method is presented for simultaneously preparing the front‐side boron emitters and the rear‐side TOPCon structures through continuous plasma enhanced chemical vapor deposition of the precursor layers followed by one‐step high‐temperature annealing. The front‐side boron emitters are fabricated using a stack of nano‐SiOx/B‐doped a‐Si:H layers as the boron source, which can avoid the formation of the stacking faults and lower the annealing temperature to match the rear‐side TOPCon fabrication processes. The rear‐side TOPCon structure, consisting of a plasma‐assisted N2O oxidation (PANO) SiOx and a nitrogen‐doped a‐Si:H(n+), is used to match the B diffusion temperature with high‐quality passivation. The precursor TOPCon cell without electrodes features excellent passivation with the highest implied open‐circuit voltage (iVoc) of 726 mV. As a result, the proof‐of‐concept TOPCon SCs exhibit a remarkable efficiency of 24.07%. This work proposes a flexible and elegant process to prepare high‐efficiency TOPCon devices, which shows great potential for application in the PV industry.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Application of Si-related Ultrathin (∼1 nm) Films to Crystalline Silicon Solar Cells

Ultrathin (∼1 nm) films have been widely used for high-efficiency crystalline silicon (c-Si) solar cells such as tunnel oxide passivated contact (TOPCon) solar cells. In this article, we present our recent results for the applications of ultrathin silicon oxide (SiOx) and silicon nitride (SiNx) films to c-Si solar cells. The following topics are reviewed. 1) Ultrathin SiNx can be utilized for passivating contacts instead of SiOx in the TOPCon structure. 2) The addition of SiOx between c-Si and thick catalytic-chemical-vapor-deposited (Cat-CVD) SiNx significantly improves the quality of surface passivation. 3) Ultrathin Al-doped SiOx films formed just by dipping in Al(NO3)3 solution on c-Si provide strong upward band bending due to negative fixed charges, which can be used for hole-selective contacts.

Cover Image

The cover image is based on the Research Article Atomic scale controlled tunnel oxide enabled by a novel industrial tube-based PEALD technology with demonstrated commercial TOPCon cell efficiencies > 24% by Baochen Liao et al., https://doi.org/10.1002/pip.3627.

Crystalline Silicon (c-Si)-Based Tunnel Oxide Passivated Contact (TOPCon) Solar Cells: A Review

Contact selectivity is a key parameter for enhancing and improving the power conversion efficiency (PCE) of crystalline silicon (c-Si)-based solar cells. Carrier selective contacts (CSC) are the key technology which has the potential to achieve a higher PCE for c-Si-based solar cells closer to their theoretical efficiency limit. A recent and state-of-the-art approach in this domain is the tunnel oxide passivated contact (TOPCon) approach, which is completely different from the existing classical heterojunction solar cells. The main and core element of this contact is the tunnel oxide, and its main role is to cut back the minority carrier recombination at the interface. A state-of-the-art n-type c-Si-based TOPCon solar cell featuring a passivated rear contact was experimentally analyzed, and the highest PCE record of ~25.7% was achieved. It has a high fill factor (FF) of ~83.3%. These reported results prove that the highest efficiency potential is that of the passivated full area rear contact structures and it is more efficient than that of the partial rear contact (PRC) structures. In this paper, a review is presented which considers the key characteristics of TOPCon solar cells, i.e., minority carrier recombination, contact resistance, and surface passivation. Additionally, practical challenges and key issues related to TOPCon solar cells are also highlighted. Finally, the focus turns to the characteristics of TOPCon solar cells, which offer an improved and better understanding of doping layers and tunnel oxide along with their mutual and combined effect on the overall performance of TOPCon solar cells.

TOPcon route with quantum wells in GaInP/Si dual junction cell for efficiency enhancement

The GaInP/Si dual junction solar cell with Quantum Well and TOPCon technology has achieved 41.91 % efficiency in the simulation model. Quantum wells are proven to enhance the short circuit current without any significant degradation of open circuit voltage. The voltage preservation measure (for minimum reduction in open circuit voltage) is applied in design of Quantum well solar cell with the improvement in short circuit current, therefore the overall efficiency of dual junction cell is enhanced. In this work, the GaInP/Si dual junction solar cell is proposed by incorporating the InP quantum wells in the p-i-n region of GaInP top cell. Also, the TOPCon technology is applied at the rear side of the bottom c-Si solar cell. The quantum well increases the absorption of sub-bandgap photon energy. The buffer layer reduces the misfits between the lattice mismatched layers and tunnel oxide provides excellent passivation mechanism to increase the open circuit voltage. The ultrathin oxide layer provides extremely high electric field as described by the MIS tunneling theory. The electron and hole bound state energy and wavefunctions provides “miniband” formation and charge carrier trapping. The formation of type-A band structure in quantum well region and excellent electron mobility results in enhanced carrier transport. The GaInP/Si integrated model achieves efficiency of 33.30 % when the quantum wells are incorporated in the top cell. When the Combination of both QWs (in top cell) and TOPCon technology (in bottom cell) is applied, the model achieves 41.95 % efficiency. This model provides an excellent route toward achieving the 45 % efficiency limit of III-V/Si dual junction 2-terminal solar cell. The industry standard Silvaco TCAD platform is used for the calculation of the performance characteristics in AM1.5G environmental condition.

Charge trapping effects in nonvolatile memory cells with HfO2/Al2O3 nanolaminated trapping layer

The charge trapping effects in memory cells with HfO2/Al2O3 nanolaminated stacks with two different thicknesses (2.4 and 3.5 nm) of the tunnel SiO2 layer were investigated. The HfO2/Al2O3 stacks were fabricated by atomic layer deposition and received post deposition annealing in O2. The structures with 3.5 nm tunnel oxide were found to provide higher density of trapped charges. The obtained trapped negative charge density is -3.56×10−6 C/cm2 and the positive one is 4.03×10−6 C/cm2. It is demonstrated that the electron trapping is significantly influenced by the amount of available electrons in the inversion layer. Under illumination, pulses with duration of 1 ms could provide trapped negative charge density equal to ~60% the value obtained at 10 s duration, where a saturation of the trapped charge is found. The hole trapping is not influenced by the illumination of capacitors and it is found to be slower than the electron one. Some aspects of the trapping process as well as some of the peculiarities in the capacitance-voltage curves obtained in the course of the measurements are briefly discussed.