Abstract
The effects of geometry and cycling are evaluated for charge-trapping NAND memory devices with SiON tunneling layers. Processing splits include SiON tunneling layers with and without H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> high-pressure annealing. Programmed and erased devices were irradiated up to 500 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with 10-keV X-rays. Excellent retention and endurance are demonstrated for these devices before and after irradiation. Scaling devices to smaller dimensions enhances program/erase efficiency and radiation tolerance.
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