TFET Research Articles

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain & gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.

Sensitivity analysis of an inverted T-shaped vertical tunneling field effect transistor biosensor based on inserted finger type

This paper presents a biosensor based on a finger-inserted inverted T-shaped vertical tunneling field effect transistor (FP-T-TFET). In order to improve the sensitivity and performance of the biosensor, a finger-inserted contact between the source and the channel is used. A comparative analysis between the biosensor based on FP-T-TFET and conventional inverted T-shaped TFET (T-TFET) is simulated for the electrical properties and sensitivity of neutral biomolecules with different dielectric constants and charged biomolecules with different charge densities. The noise analysis of the proposed structure is also performed. Then, the effects of insertion finger distribution, cavity size and filling volume on the performance of FP-T-TFET are investigated. Finally, the structure was subjected to linear analysis, in which the pearson coefficient was 0.92, indicating that the structure has good linear correlation. The results show that the FP-T-TFET biosensor has higher sensitivity in detecting various neutral and charged biomolecules. All device simulations were performed in the TCAD environment with a well-calibrated structure.

Analysis of etched drain based Cylindrical agate‐all‐around tunnel field effect transistor based static random access memory cell design

AbstractThis paper aims to propose a novel method for designing an static random access memory (SRAM) cell using an etched drain based Cyl GAA TFET with a hetero‐substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing static noise margin (SNM) as well as N‐curve methods. With respect to the 16 nm MOSFET based SRAM cell, the proposed device‐based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in static voltage noise margin (SVNM), an 8.623% increase in static current noise margin (SINM), an 8.152% increase in write trip voltage (WTV), a 12.86% increase in write trip current (WTI), a 27.62% increase in static power noise margin (SPNM), and a 19.95% increase in write trip power (WTP). The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems.

Modelling of Cut-off Frequency of Armchair Graphene Nanoribbon Tunnel Field Effect Transistor Using Transfer Matrix Method

Graphene is considered as a promising two-dimensional material for electronic device applications due to its high charge carrier mobility and it is extremely thin in size. As a material, graphene has great potential for the development of high-speed nano electric devices. Graphene can be used as a channel material in Tunnel Field Effect Transistor (TFET). In this study, the cut-off frequency of the armchair graphene nanoribbon tunnel field effect transistor (AGNR-TFET) device was modelled quantum mechanically. The solution of the Dirac-like Hamiltonian and Poisson equations self-consistently is used to determine the potential profile of device and the transmittance is calculated using the transfer matrix method (TMM). The Landauer formulation with the help of Gauss Legendre Quadrature Method (GLQM) is used to calculate the tunnelling current and the cut-off frequency of AGNR-TFET. The calculation results showed that the cut-off frequency increased as the drain voltage increased, while the increase in channel length and the N-index graphene made the cut-off frequency decreased. Moreover, the thicker the oxide layer could increase the cut-off frequency and the higher the temperature on the device would reduce the cut-off frequency.

Dielectric Modulated Nanotube Tunnel Field-Effect Transistor with Core-Shell Cavity as a Label-Free Biosensor: Proposal and Analysis.

Dielectric Modulated Field-Effect Transistors (DMFETs) have emerged as promising candidates for label-free bioanalyte detection. However, the inherent short-channel effects in conventional DMFETs increase their static power dissipation significantly and limit their scalability and sensitivity. Therefore, FETs based on alternate conduction mechanism such as tunneling (TFETs), which are immune to the short-channel effects, appear to be a lucrative alternative to the MOSFETs for biosensing application. In this work, we propose a novel Dual Cavity Dielectric Modulated Nanotube Tunnel FET (DCDM NTTFET)-based label-free biosensor consisting of a Ge source and nanocavities within the core as well as a shell gate stack, which not only outperforms the conventional MOSFET and advanced nanowire (NW) TFET-based biosensors in terms of energy-efficiency and scalability but also exhibits a significantly high drain current sensitivity (SION = 2.9 × 108) and a threshold voltage sensitivity (SVth = 0.85), and a considerably high selectivity of more than 6 orders of magnitude. We also perform a comprehensive design space exploration for the proposed DCDM NTTFET and provide necessary design guidelines to further improve its performance considering the practical artifacts such as steric hindrance.

Transport in a Two-Channel Nanotransistor Device with Lateral Resonant Tunneling.

We study field effect nanotransistor devices in the Si/SiO2 material system which are based on lateral resonant tunneling between two parallel conduction channels. After introducing a simple piecewise linear potential model, we calculate the quantum transport properties in the R-matrix approach. In the transfer characteristics, we find a narrow resonant tunneling peak around zero control voltage. Such a narrow resonant tunneling peak allows one to switch the drain current with small control voltages, thus opening the way to low-energy applications. In contrast to similar double electron layer tunneling transistors that have been studied previously in III-V material systems with much larger channel lengths, the resonant tunneling peak in the drain current is found to persist at room temperature. We employ the R-matrix method in an effective approximation for planar systems and compare the analytical results with full numerical calculations. This provides a basic understanding of the inner processes pertaining to lateral tunneling transport.

Exploring the Potential of Tunnel Field-Effect Transistors in Biomedical Devices: A Comprehensive Survey

Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being.

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 μm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Performance assessment of SiGe extended four corner source TFET for biosensing applications

In this paper, the performance of a novel SiGe extended four corner source tunneling field–effect transistor (SiGe EFCS TFET) based dielectrically modulated label-free biosensor has been investigated for biosensing applications. Using a combination of heterostructure (SiGe/Si) and extended four corner source (EFCS) lead to increased band–to–band tunneling (BTBT) probability, improved gate control and superior drain current sensitivity for biomolecule conjugation in comparison with a conventional TFET and Si EFCS TFET structures of similar dimensions. The influence of both the charge–neutral and charged biomolecules on the sensitivity performance is investigated using the Silvaco TCAD ATLAS semiconductor device simulator with a calibrated nonlocal BTBT model. Four different kinds of biomolecules such as Streptavidin, Ferro–cytochrome c, Keratin and Gelatin with various charge density values were used for this purpose. In order to model steric hindrance effects in partially filled cavities, in addition to various fill factors, four different step profile patterns have considered such as convex, concave, decreasing and increasing step profiles. Also, the dependence of the nanogap cavity properties on the sensing performance in terms of the length and thickness is investigated. A maximum drain current sensitivity of 1.69 × 105 is achieved in SiGe EFCS TFET for Gelatin biomolecules in a fully filled nanogap cavity at overdrive and drain voltages of 0.5 V.

Design Points of InGaAs MFMIS Tunnel FET for Large Memory Window and Stable Ferroelectric Memory Operation

Design Points of InGaAs MFMIS Tunnel FET for Large Memory Window and Stable Ferroelectric Memory Operation

Impact of SiGe pocket on different shape TFET structures for gas sensing application

Gas sensing requires highly sensitive and selective sensor technologies for environmental monitoring, industrial safety, and public health objectives. Although conventional MOSFET-based gas sensors are widely utilized, their detection of low quantities of gases, such as ammonia, is hindered by a number of severe constraints. TFET is emerged as the better device than MOSFET, particularly for the sensing applications. In this work we discussed the source engineered and shape engineered techniques to improve the performance of TFETs, specifically for ammonia gas detection. Comprehensive simulations on SILVACO TCAD and compared the four TFET structures SiGe-pocket DGTFET, SiGe-pocket vertical TFET SiGe-pocket Z-shape TFET, and SiGe-pocket U-shape TFET structure on the basis of various electrical characterization parameters. Significant improvements in efficiency and sensitivity are obtained by adjusting the work function of the molybdenum (4.40–4.60 eV) catalytic gate metal to find the optimal values. The findings reveal that the SiGe-pocket U-shape TFET structure exhibits superior performance, demonstrating an ION of 8.01 × 10−4 A/μm, an ION/IOFF ratio of 1.25×1013, and an OFF current sensitivity (SOFF) of 1.262. These results highlight the enhanced sensitivity and efficacy of the proposed SiGe-pocket U-shape tunnel FET in ammonia gas sensing applications, making it a promising candidate for practical uses in environmental monitoring and industrial safety.

Low-power ternary inverter using vertical tunnel field-effect transistor with pocket

ABSTRACT This paper proposes a vertical tunnel FET with pocket (VP-TFET)-based standard ternary inverter (T-inverter) model for low-power applications. Using TCAD Sentaurus tool and mixed-mode simulations, it is verified that the device can exhibit T-inverter voltage transfer characteristics (VTCs) with three steady output voltage levels when the doping length and concentration of the pocket are optimized The device’s T-inverter characteristics are achieved by employing channel-channel and source-channel tunnelling mechanisms. Current matching is crucial for n-/p–type devices to produce a steady third output voltage state. The proposed ternary inverter’s static noise margin (SNM) and static and dynamic power dissipations are computed to be 220 mV, 4.8 × 10−12 W, and 4 × 10−12 W, respectively, which assures better noise immunity and low power consumption compared to other models.

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Tunnel field-effect transistors (TFETs) are expected to be used as a next-generation low-voltage switching device. The TFETs can lower the subthreshold slope (SS) below the physical limit (SS = 60 mV/dec at room temperature) in conventional MOSFETs. Here we demonstrated InAs nanowire (NW)/Si heterojunction vertical gate-all-around (VGAA) TFETs on silicon-on-insulator (SOI) (111) substrates toward vertical integrated circuit applications. The vertical InAs NW channels were grown by selective-area growth on thin SOI(111) substrates.

Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controllability under low supply voltage. In addition, III-V NWs/Si tunnel junctions, which are formed by the direct integration of vertical III-V NWs on Si, can be utilized as VGAA tunnel FETs (TFETs) for low-power switch. Here we report on direct integration of vertical InGaAs NWs on silicon-on-insulator (SOI) substrates by selective-area growth and demonstrations of InGaAs NW-channel VGAA transistors (FETs and TFETs) on SOI.

A VERY LOW BANDGAP LINE-TUNNEL FIELD EFFECT TRANSISTOR WITH CHANNEL-BURIED OXIDE AND LATERALLY DOPED POCKET

Low bandgap and line tunneling techniques have demonstrated the most effectiveness in enhancing the on-current of tunnel field-effect transistors (TFETs). This study examines the mechanisms and designs of channel-buried oxide and a laterally doped pocket for a very low bandgap line-TFET. Numerical TCAD simulations show that the channel-buried oxide is needed to prevent off-state lateral tunneling while still maintaining the on-state vertical tunneling. The buried oxide pillar should be high so that the channel is thin, about 10 nm thick, to completely suppress the tunneling leakage. The dopant pocket is required to trigger the line tunneling earlier than the point tunneling to improve the subthreshold swing and on-current. Increasing the pocket concentration or decreasing the pocket thickness both cause an increase not only in the vertical band bending but also in the effective gate-insulator thickness. Because of the trade-off between these two operation parameters, for a given thickness/concentration, there exists an optimal concentration/thickness of the pocket to maximize the on-current. The on-current is optimized using a heavy, thin pocket, for which the band bending is maximized and the effective gate-insulator thickness is minimized. For the fabrication feasibility using existing doping techniques, the pocket concentration and thickness should be 1019 cm-3 and 4 nm, respectively, to maximize the on-current of the InAs line-TFET.

Realizing n-type carbon nanotubes via halide perovskite nanowires Cs4MX5 inner filling

N-type carbon nanotubes (CNTs)-based field-effect transistors (FETs) have huge potential applications in low-power consumption tunnel FETs. However, the low-work function metal electrodes can achieve n-type CNTs, but they are easily oxidized due to poor environmental stability. Therefore, based on first-principles calculations, we proposed halide perovskite nanowires Cs4MX5 (M = Pb, Sn; X = Cl, Br, I) inner filling to achieve n-type single-walled CNTs (SWCNTs). The results indicated that all the perovskite nanowires located at the center of the SWCNTs possess high stability. Moreover, the diameter of SWCNTs is a crucial factor affecting the inner filling of perovskite nanowires with an optimal diameter of about 1.4 nm. Furthermore, all the perovskite nanowires Cs4MX5 are excellent electron donors, and the largest charge transfer is up to 1.72 e/nm for Cs4SnI5. Their interaction mechanism reveals that the low work function and the large internal bandgap are two important factors for cubic-phase nanowires to realize the n-type CNTs. Our findings provide some candidate materials and a feasible way to achieve n-type CNTs for applying CNTs-based FETs.

Design and Simulation of a High-Performance Tunneling Field Effect Transistor-Based Biosensor Using a Heterojunction Electron-Hole Bilayer

Abstract This study introduces a novel dielectrically-modulated heterojunction electron-hole bilayer tunnel field-effect transistor (DM-HEHBTFET) for bio-sensing applications. The device features a Ga0.85Sb0.15As/Ga0.8In0.2As heterojunction and a p-type pocket in the channel, achieving a remarkably low threshold voltage (VT) of 20 mV, an average subthreshold slope (SS) of 5.7 mV/dec, and a leakage current (IOFF) as low as 5 × 10⁻¹¹ A/μm. The staggered bandgap in the heterostructures enhances electric field control, enabling lower gate voltage operation. Furthermore, the strategically positioned nanogap cavities in non-overlapping regions of the top and bottom gates effectively mitigate gate control issues over the channel, ensuring improved device performance. A modified design, the modified DM-HEHBTFET, is also proposed, featuring source and drain regions engineered with Ga0.85Sb0.15As/Ga0.8In0.2As heterojunctions. This design mitigates leakage current and improves the average subthreshold slope (SS). For biomolecules with a dielectric constant of 12, the modified biosensor exhibits a drain current sensitivity (Scurrent) of 2.6e4, average SS=2.7 mV/dec, and IOFF=1e-12 A/μm. The device's performance is assessed by examining steric hindrance and band tailing effects. The modified biosensor outperforms recent DM-TFET biosensors, making it a promising candidate for low-power, high-switching speed bio-sensing.

An energy efficient leaky integrate and fire neuron using Ge-source TFET for spiking neural network: simulation analysis

The basic building block of neural network is a device, which can mimic the neural behavior. The spiking neural network (SNN) is an efficient methodology in terms of power and area. Due to the excess energy consumption and larger area, various spintronic neural devices are unfit for neuron applications. In this article, we have implemented Ge source based Tunnel FET (TFET) for ultralow energy spike generation using TCAD simulator. It is seen that Ge source TFET has signature spiking frequency in THz range versus input voltage curve of an artificial biological neuron. The simulated device deploy the leaky integrate and fire (LIF) technique for generation of neurons. The simulation result highlights that the energy of device is 1.08 aJ/spike, which is several order less than existing neural based FET devices in literature.

Z-shaped gate tunnel FET with graphene channel: An extensive investigation of its analog and linearity performance

This work analyzes a graphene channel Z-shaped gate tunnel FET's (ZTFET) analog, and linearity performance. This research aims to introduce graphene with a two-dimensional honeycomb structure that is anticipated to be a strong challenger for the upcoming generation of semiconductor devices. The ZTFET with graphene channel provides a 3-decade increase in ON current, indicating a notable improvement in gate capacitance and transconductance compared to the conventional silicon channel. This improvement further leads to better linearity and analog/RF performance. We delved into various linearity and Radio Frequency (RF) figure-of-merits, including gmn, VIP2, VIP3, IIP3, 1‐dB compression point, GBWP, TFP, unity gain cut‐off frequency, and maximum oscillation frequency. The results of the new GC-ZTFET are compared with those of the traditional ZTFET to establish its superiority. The GC-ZTFET outshines other device structures when speaking of linearity, RF performance, and current-carrying capability.