TFET Research Articles

Negative capacitance source pocket double gate tunnel FET as a label-free dielectrically modulated biosensor

Abstract This article examines the potential use of Negative Capacitance Source Pocket Double Gate Tunnel Field Effect Transistor (NC-SP-DGTFET) as a biosensor capable of detecting the biomolecules present in the nanocavity. The proposed biosensor incorporated a gate dielectric engineering along with the channel engineering method and asymmetrical doping at source and drain regions. In addition, a nanocavity is formed by selectively removing a section of the gate dielectric at the source and drain ends to accompany the biomolecules in the device. The biosensing performance measures Threshold Voltage Sensitivity (S_(V_th )), ION/IOFF Current Ratio Sensitivity (S_(I_oN/I_OFF )), and Drain Current Sensitivity (S_(I_DS )), with 60.3, 372.3, and 395.4 respectively are observed with neutral charge of biomolecules. The investigation involves biomolecules with positive and negative charges, which are tested under different dielectric constants in the nanocavity. In addition, an extensive investigation of a partially filled nanocavity caused by steric hindrance has been presented to capture the current situation. The study examined several scenarios with partially filled nanocavities to analyze the sensitivity characteristics, including convex, concave, increasing, and decreasing step profiles, as well as the positioning of the probe in an asymmetric manner. The study compares several sensitivity characteristics of the NC-SP-DGTFET with existing biosensors to determine the effectiveness of the proposed biosensor. The NC-SP-DGTFET biosensor outperforms traditional TFET-based biosensors by using a ferroelectric material as the oxide material. This choice of material enhances the subthreshold slope, increases gate control over the channel, and demonstrates its suitability for low-power biosensor design.

Dual Subgate-Assisted Tunneling Field-Effect Transistor Based on Regulation of MoS2 Channel Surface Potential

Dual Subgate-Assisted Tunneling Field-Effect Transistor Based on Regulation of MoS₂ Channel Surface Potential

Sensitivity Analysis of Biosensor-Based SiGe Source Dual Gate Tunnel FET Having Negative Capacitance

Sensitivity Analysis of Biosensor-Based SiGe Source Dual Gate Tunnel FET Having Negative Capacitance

Performance assessment of a JF-CP-TFET for hydrogen gas sensing applications

Abstract In this paper, a junction-free charge plasma tunnel field-effect transistor (JF-CP-TFET) is proposed and analyzed for the first time to sense hydrogen (H2) gas. Using junction-free and charge-plasma approaches, the proposed JF-CP-TFET-based sensor minimizes random dopant fluctuations, a large thermal budget requirement, and complex processes in the semiconductor sensor production process. The sensing performance of the JF-CP-TFET-based gas sensor is demonstrated by analyzing changes in the work function of the gate of palladium (Pd) catalytic metals, which are proportional to the pressure of H2 gas exposed at the metal gate surface. The presence of H2 gas has been demonstrated by variations of the DC/AC parameters of the proposed sensor, such as carrier concentration, energy band, electric field, transfer characteristics, threshold voltage (VTh), and subthreshold swing (SS). The sensitivity of the JF-CP-TFET-based sensor has been evaluated in terms of drain current (IDS), ION/IOFF ratio, VTh, and SS change in the presence and absence of H2 gas molecules. The sensing capabilities of the proposed JF-CP-TFET-based gas sensor demonstrate that it could potentially be employed for H2 gas detection with excellent sensitivity and reliability.

Phosphorus-based heterojunction tunnel field-effect transistors: from atomic insights to circuit renovations.

Tunnel field-effect transistors (TFETs) are gaining interest for low-power applications, but challenges like poor drive current, delayed saturation, and ambipolarity can hinder their performance. This work proposes a dopingless heterojunction TFET (DL-HTDET) utilizing advanced materials, all based on phosphorus, to address these issues. Our approach involves a comprehensive and accurate analysis of the DL-HTDET's behavior. It employs a hybrid simulation technique integrating atomistic modeling, device simulation, and circuit design. For the first time, we use density functional theory to compute the electrical parameters of a two-dimensional material, 10-layer black phosphorus, configured in the armchair direction as the source region. InP serves as the pocket, while AlP, with its high bandgap, acts as the drain region to suppress ambipolarity. Key parameters, including bandgap, effective mass, mobility, static dielectric constant, and electron affinity, are utilized to simulate the device characteristics. Three mechanisms are considered in the device design: interband tunneling, intraband tunneling, and thermionic emission. The effect of pocket length (Lpocket) on performance is studied, and the impact of different types of interface trap charges, ranging from low to high density, is considered, and the optimized device demonstrates good durability. Additionally, the gate leakage current, which is crucial for static power consumption, is taken into account. The DC and analog/radio frequency performance of the device are evaluated. The optimized DL-HTDET achieves an ON-state current of 125 μA μm-1, a current switching ratio of 1016, an average subthreshold swing of 5.10 mV dec-1, and a transconductance of 1.47 mS μm-1. A 7T SRAM cell is implemented, demonstrating high noise margins, low delay, and ultra-low power consumption. These achievements underscore the potential of the proposed device for high-speed, ultralow power applications.

Interface engineering of van der Waals heterostructures towards energy-efficient quantum devices operating at high temperatures

Abstract Quantum devices, which rely on quantum mechanical effects for their operation, may offer advantages, such as reduced dimensions, increased speed, and energy efficiency, compared to conventional devices. However, quantum phenomena are typically observed only at cryogenic temperatures, which limits their practical applications. Two-dimensional materials and their van der Waals (vdW) heterostructures provide a promising platform for high-temperature quantum devices owing to their strong Coulomb interactions and/or spin-orbit coupling. In this review, we summarise recent research on emergent quantum phenomena in vdW heterostructures based on interlayer tunnelling and the coupling of charged particles and spins, including negative differential resistance, Josephson tunnelling, exciton condensation, and topological superconductivity. These are the underlying mechanisms of energy-efficient devices, including tunnel field-effect transistors, topological/superconducting transistors, and quantum computers. The natural homojunction within vdW layered materials offers clean interfaces and perfectly aligned structures for enhanced interlayer coupling. Twisted bilayers with small angles may also give rise to novel quantum effects. In addition, we highlight several proposed structures for achieving high-temperature Majorana zero modes, which are critical elements of topological quantum computing. This review is helpful for researchers working on interface engineering of vdW heterostructures towards energy-efficient quantum devices operating above the liquid nitrogen temperature.

A high-performance capacitorless 1T-DRAM based on Z-shaped electron-hole bilayer TFET and SiGe memory window

Abstract In this paper, a novel capacitorless dynamic random access memory (Z-EHBTFET 1T-DRAM) is designed based on a Z-shaped electron-hole bilayer tunnel field-effect transistor and a SiGe memory window, and its storage performance is systematically analyzed and studied in detail through numerical simulation. A large number of electrons can be induced in the inverted L-shaped channel of Z-EHBTFET 1T-DRAM using gate 1 to create an electron-hole bilayer together with the source region, which increases the line tunneling electric field and ultimately improves the sensing margin (SM) and read current ratio (IR1/IR0). SiGe memory window helps to improve the storage capacity of holes, aiming to improve the retention time (RT) and SM. By optimizing the Ge-composition and width of the SiGe memory window, the thickness of the I-shaped channel, and the gate gap length, the SM of 2.03 μA/μm, IR1/IR0 of 3.58 × 104, and RT of 1.2 s can be obtained for Z-EHBTFET 1T-DRAM. Compared with most reported 1T1C-DRAMs and traditional 1T-DRAMs, it has better storage performance. Moreover, it can operate at a lower programming voltage while ensuring superior storage performance, making it has great application prospect in the low power consumption field.

Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects.

We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium Green's function approach. The pristine nanoribbon TFET devices with and without underlap (UL) exhibit poor performance. Introducing a H defect in the left UL region between the source and channel can drastically enhance the ON-state currents and reduce the SS to below 60 mV/decade. When the H defect is positioned far from the gate and/or at the center sites, the ON-state currents are substantially enhanced, meeting the International Technology Roadmap for Semiconductors requirements for high-performance and low-power devices with 5 nm channel length. The gate-all-around (GAA) structure can further improve the performance of the devices with H defects. Particularly for the devices with H defects near the edge, the GAA structure significantly reduces the SS values as low as 35 mV/decade. Our study demonstrates that GAA structure can greatly enhance the performance of the arsenene nanoribbon TFET devices with H defects, providing theoretical guidance for improving TFET performance based on two-dimensional material nanoribbons through the combination of defect engineering and GAA gate structures.

DC and RF Performance Optimization of Source Pocket Designed Hybrid-Dielectric Vertical Nanowire Tunnel-FET: Low Power Perspective

This article addresses a new source pocket designed hybrid-dielectric vertical nanowire tunnel-FET (SP-HD-VNW-TFET). The existence of a source pocket at the source and channel boundary is shown such that the potential barrier at the tunnel-junction is minimized which causes ON current to rise. This article studied a comparison between a SP-HD-VNW-TFET device and source pocket vertical nanowire tunnel field effect transistor (SP-VNW_TFET). Using a hetero/hybrid-dielectric material boosts the electric field, resulting in higher tunneling current (1.72 × 10−6 A μm−1). The device has undergone detailed investigation of both DC and AC characteristics like On-current, Off-current, ION/IOFF, Subthreshold-swing, VT, gm, fT, GWB, and TFP. Source Pocket engineering and Hybrid dielectric inclusion increase device properties, including on-current and subthreshold swing (SS). The device’s electrical properties have been evaluated and compared using the Sentaurus TCAD Tool.

A simple approach for integrating quantum confinement effects into TCAD simulations of tunnel field-effect transistors

A simple approach for integrating quantum confinement effects into TCAD simulations of tunnel field-effect transistors

Line-tunneling based GaP/Si heterostructure vertical gate-all-around tunnel FET for enhanced electrical performance

This study explores strategies to enhance Tunnel FET performance through innovative device geometry and heterostructure integration. The use of a GaP/Si heterostructure, combined with a heavily doped n + source pocket, significantly boosts BTBT (band-to-band tunneling). The gate, which completely surrounds the source, induces line-tunneling and improves gate control over the tunnel junction, further contributing to enhanced device performance. The incorporation of a gate-drain underlap architecture and a vertically oriented design effectively suppresses ambipolar and leakage currents, resulting in an increased current ratio, reduced subthreshold slope (SS), and a minimized device footprint. Comparative analysis with existing TFET architectures shows that the optimized device achieves promising results, including an average SS of 13 mV/decade, an off-current (Ioff) of 2.36 × 10-17 A, an on-current (Ion) of 2.1 × 10-5 A, and an ambipolar current (Iamb) of 3.28 × 10-16 A.

Dual‐Layer‐Per‐Array Operation Using Local Polarization Switching of Ferroelectric Tunnel FETs for Massive Neural Networks

AbstractA novel dual‐layer‐per‐array (DLPA) operation is proposed and experimentally demonstrated by using ferroelectric tunnel field‐effect transistors (FeTFETs) as synaptic transistors for high‐density and low‐power neuromorphic computing applications for the first time. Through local polarization switching (LPS), two distinct synaptic weight sets are stored and processed by utilizing the symmetrical and independent forward and ambipolar current regions within a single FeTFET. The stored weights of each region are multiplied by input gate voltages in the two‐layer operation modes of TFETs: forward and ambipolar layer, enabling separate vector‐matrix multiplication (VMM) operations within a single device array and doubling computational density. It is expected that the DLPA operation of FeTFETs will facilitate the implementation of large neural networks by reducing the footprint of conventional neuromorphic hardware by 50%.

Subthreshold slope optimization for pentacene based organic tunnel field effect transistor

Conventional Organic Thin Film Transistors (OTFTs) face significant challenges. Short-channel effects prevent current saturation when scaled to the nanoscale, while the thermionic transport mechanism limits the subthreshold swing to values above 60 mV/dec. To overcome these limitations, a Doped Lateral Organic Tunnel Field Effect Transistor (DL O-TuFET) is proposed. This work examines the influence of source and drain doping on device performance. The higher source doping enhances tunneling probability, while moderate drain doping reduces OFF-current and improves subthreshold swing. Furthermore, the impact of trap density in the active material on device characteristics is investigated. Key performance metrics, including threshold voltage, subthreshold swing, ON/OFF ratio, and RF parameters, are quantitatively analyzed. Simulations using Silvaco TCAD reveal that an optimized source and drain doping of 1 x 1021 cm−3 and 1 x 1019 cm−3, respectively, yields promising results. The device exhibits a threshold voltage of −0.963 V, a subthreshold swing of 12.5 mV/decade, an ON/OFF ratio in the range of 1017, a maximum electric field of 5.41 × 107 V/cm, and a maximum band-to-band tunneling rate of 7.94 x 1032/cm3s. These values contribute to a maximum ON-current of 83.6 μA, making the DL O-TuFET a viable alternative to conventional OTFTs. Moreover, a maximum cut-off frequency of 0.66 GHz demonstrates its suitability for higher-speed applications.

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Introduction Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms.Experimental procedureFirst, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature.ResultsThe growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface.Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs.The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter.We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed.[1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432[2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480

Analytical modeling of III-V heterojunction source-all-around vertical tunnel FET and its inverter circuit application

Abstract This paper presents a comprehensive analytical modeling framework for the III-V heterojunction source-all-around vertical tunnel field-effect transistor (SAA V-TFET). Using Kane’s model, our approach involves solving Poisson’s equations to obtain a continuous surface potential profile, followed by the derivation of drain current. These models demonstrate excellent accuracy across all operating regions, precisely predicting the potential profile, output, and transfer characteristics of SAA V-TFETs. We implemented the models in MATLAB and validated them against Sentaurus TCAD simulations. Furthermore, we present a comprehensive performance analysis of SAA V-TFET-based digital inverters.

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain &amp; gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.&amp;#xD;

III–V heterostructure tunnel field-effect transistor operation at different temperature regimes

Tunnel field-effect transistors (TFETs) are a potential alternative to MOSFETs for low-temperature electronics. We provide an in-depth experimental characterization of TFETs analyzing the fundamental physical behavior at different temperature regimes. TFET characteristics from 13 to 300 K both in forward and reverse bias are discussed by employing a variation in InAs/InGaAsSb/GaSb heterojunction vertical nanowire devices. Evaluation of the TFET Negative Differential Resistance (NDR) characteristics at different temperatures is established as a technique to probe the dopant incorporation. It is observed that the temperature dependence of the Fermi degeneracy and Fermi-Dirac distribution largely influences the transistor performance at each operating temperature. Our investigation reveals that the TFETs demonstrate lower subthreshold swing than the physical limit of MOSFETs above 125 K. For low-temperature applications, the devices can be operated down to a low operating bias of 0.1 V, while for high temperature, a larger bias of 0.3 V is preferred.

Ultra-sensitive dengue NS1 protein detection via asymmetric source-drain, heterojunction and dual-dielectric cavities in a uniform tunnel FET biosensor

In this paper, we present a unique Asymmetric Source-Drain Heterojunction Dual-Dielectric Uniform Tunnel Field Effect Transistor (A-SD-HJ-DD-UTFET) based biosensor tailored for the early detection of dengue NS1 protein during the acute phase of infection offering early diagnosis and potentially life-saving intervention. The proposed biosensor design features simplified fabrication, a narrow drain region, and a dual material control gate, enhancing specificity and sensitivity for dengue virus detection. Using a heterojunction configuration, this device optimizes electron flow for improved detection accuracy. The roles of Tunnel Gate (TG) and Auxiliary Gate (AG) are studied in terms of band energy, electric field, electrostatic potential, and other sensitivity parameters. Sentaurus TCAD tool is utilized for analyzing the characteristics of the proposed A-SD-HJ-DD-UTFET biosensor. Simulation results indicate that the designed A-SD-HJ-DD-UTFET biosensor achieves a superior Subthreshold Swing (SS) of 15.4 mV/dec and an enhanced ION/IOFF sensitivity of about 2.25 × 10¹¹ with a maximum ON and minimum OFF state currents of 2.28 × 10–4 A/μm and 1.28 × 10–16 A/μm respectively for detecting NS1 protein of dengue. Additionally, it boasts a high switch ratio in the order of 1012. The proposed biosensor outperforms conventional devices, including the state-of-the-art Junctionless (JL)-TFET biosensors. The superior electrical characteristics of the proposed A-SD-HJ-DD-UTFET biosensor make it a promising device for early detection of the dengue NS1 protein, providing a potent solution for mitigating the spread of dengue infections.

Study and analysis of a dielectric-modulated vertical tunnel FET biosensor using dual material gate

A bimetal gate heterogeneous dielectric vertical tunnel field-effect transistor (BG-HD-VTFET) biosensor has been investigated in this paper for the first time using engineered-gate concept, where nanogaps are introduced under tunnel gate (TG) to detect biomolecules near the device surface. To improve the detection performance of BG-HD-VTFET, an overlap is designed between source and pocket region, and the sensing ability of BG-HD-VTFET with and without overlap is compared in details. Further, an auxiliary gate (AG) is added for the proposed two devices to optimize the electrical characteristics, and the y composition of GaAsySb1-y in pocket region is optimized to enhance ON-state current, and then different neutral and charged biomolecules are considered to simulate device-level gate effects. In addition, the influence of different dielectric constant at fixed charge density is studied and the length of overlap is optimized. Simulation results show that the maximum sensitivity of BG-HD-VTFET with and without overlap can reach 3.3 × 103 and 1.9 × 103, respectively.

Enhanced Performance of Dual Material Double Gate Negative Capacitance Tunnel Field Effect Transistor (DMDG‐NC‐TFET) via HZO Ferroelectric Integration for Improved Drain Current and Subthreshold Swing

ABSTRACTThis paper developed the novel structure of a dual material double gate negative capacitance tunnel field effect transistor (DMDG‐NC‐TFET) using HZO ferroelectric material. This study systematically improved the drain current and subthreshold swing (SS) by inducing a negative capacitance effect in a gate stack. The proposed gate oxide structure is a stack configuration of ferroelectric material, and high‐k dielectric to improve gate control. The Landau–Khalatnikov (LK) equation is used to solve the Poisson equation and get an accurate estimate of the channel potential. Kane's model is used for band‐to‐band generation rate calculation. For modelling the drain current, the band‐to‐band tunnelling (Gbtbt) generation rate is integrated using the entire device volume. The impact of varying ferroelectric thickness in the proposed structure has been investigated with the simulated results. The outcomes demonstrate that the device can obtain better improvements in ON current and SS, compared to conventional DMDG‐TFET. By contrasting the analytical results with the outcomes of the TCAD simulation, the effectiveness of the proposed methodology has been demonstrated.