True Single Phase Clocking Flip-flop Research Articles

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

New Power-efficient Flip-flop based on a True Single-phase Clock and Robust to Single-node Upsets

As the size of technology shrinks, its immunity to the space radiation environment decreases. A single-event transient (SET) induced by radiation can cause permanent damage to devices. Therefore, engineers have been researching radiation-hardened flip-flops or latches that are robust to soft errors. This paper proposes a true-single-phase-clock (TSPC)-based single-node-upset (SNU)-tolerant flip-flop, which is robust to SNUs and even faster than conventional DFFs. This flip-flop consists of two modules of TSPC flip-flops, except for inverters, and a Muller C-element. It has only 22 transistors, which makes it area-efficient. Moreover, the proposed flip-flop uses a TSPC; hence, the clock-to-Q delay is 10% less than the conventional DFF.

Power optimisation of both a high‐speed counter and a retiming element for 2.4 GHz digital PLLs

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.

A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS

In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static data retention based on two forward-conditional feedback loops, without increasing the clock load, in comparison to the baseline TSPC architecture. The proposed FF was implemented for ultralow-voltage operation in 28-nm fully-depleted Silicon-on-Insulator (FDSOI) CMOS. The performance of the proposed FF extracted from measurements of clock dividers is compared with reference designs, including the conventional master–slave (M–S) FF, the baseline TSPC FF, and a recently proposed retentive TSPC FF. Compared with the conventional M–S FF, the proposed FF shows, respectively, 5%, 40%, and 30% improvements at 0.4 V in maximum frequency, energy/cycle, and leakage power.

Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier

ABSTRACTThe present study examines double pass-transistor logic (DPL) and evaluates the performance of a proposed DPL-based 8b × 8b wave-pipelined pair-wise multiplier. It then compares some of its critical performance-parameters with a Normal-Process-Complementary-Pass-transistor-Logic (NPCPL) based design. Double transmission properties with balanced input capacitance of DPL gate, is the focus of the present work to improve multiplier performance like throughput and noise margin at reduced supply. In DPL both N-type and P-type devices help balanced transmission of logic ‘1’ and logic ‘0’ that in turn reduces data-dependent delay variation, and is therefore suitable for time equalised applications. Pulse-triggered TSPC (true single phase clocking) flip-flop (PTTFF) is once again used to design I/O registers of the multiplier for the advantages already stated in the previous work. The design is optimised and validated on TSMC-0.18 µm single-poly double-metal (SPDM) CMOS technology at 25°C temperature. Parameters for comparison include power-dissipation, throughput, latency, area and noise-margin under 2 V, 1.8 V and 1.5 V supply.

Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect

With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

In this study, a low-power, high-speed, layout-efficient 8 b × 8 b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 μm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented.

LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS

In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.