New Power-efficient Flip-flop based on a True Single-phase Clock and Robust to Single-node Upsets

Abstract

As the size of technology shrinks, its immunity to the space radiation environment decreases. A single-event transient (SET) induced by radiation can cause permanent damage to devices. Therefore, engineers have been researching radiation-hardened flip-flops or latches that are robust to soft errors. This paper proposes a true-single-phase-clock (TSPC)-based single-node-upset (SNU)-tolerant flip-flop, which is robust to SNUs and even faster than conventional DFFs. This flip-flop consists of two modules of TSPC flip-flops, except for inverters, and a Muller C-element. It has only 22 transistors, which makes it area-efficient. Moreover, the proposed flip-flop uses a TSPC; hence, the clock-to-Q delay is 10% less than the conventional DFF.