Abstract
In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static data retention based on two forward-conditional feedback loops, without increasing the clock load, in comparison to the baseline TSPC architecture. The proposed FF was implemented for ultralow-voltage operation in 28-nm fully-depleted Silicon-on-Insulator (FDSOI) CMOS. The performance of the proposed FF extracted from measurements of clock dividers is compared with reference designs, including the conventional master–slave (M–S) FF, the baseline TSPC FF, and a recently proposed retentive TSPC FF. Compared with the conventional M–S FF, the proposed FF shows, respectively, 5%, 40%, and 30% improvements at 0.4 V in maximum frequency, energy/cycle, and leakage power.
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