Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier

Abstract

ABSTRACTThe present study examines double pass-transistor logic (DPL) and evaluates the performance of a proposed DPL-based 8b × 8b wave-pipelined pair-wise multiplier. It then compares some of its critical performance-parameters with a Normal-Process-Complementary-Pass-transistor-Logic (NPCPL) based design. Double transmission properties with balanced input capacitance of DPL gate, is the focus of the present work to improve multiplier performance like throughput and noise margin at reduced supply. In DPL both N-type and P-type devices help balanced transmission of logic ‘1’ and logic ‘0’ that in turn reduces data-dependent delay variation, and is therefore suitable for time equalised applications. Pulse-triggered TSPC (true single phase clocking) flip-flop (PTTFF) is once again used to design I/O registers of the multiplier for the advantages already stated in the previous work. The design is optimised and validated on TSMC-0.18 µm single-poly double-metal (SPDM) CMOS technology at 25°C temperature. Parameters for comparison include power-dissipation, throughput, latency, area and noise-margin under 2 V, 1.8 V and 1.5 V supply.